# Clock and Data Recovery/Introduction/Models can only be linear..

Parts of this page are based on materials from: Wikipedia/Simulation. |

## The reference models

[edit | edit source]Today' CDR circuits are implemented using a PLL architecture, and are realized mostly or entirely with CMOS digital circuitry.

The complexity of the circuitry is often so large that -not unfrequently- the architecture is not clearly identified and consequently the circuit operation is not fully understood.

It is very useful to make reference to relatively simple circuits that implement the CDR in a first or second order PLL architecture.

The comprehension of the characteristics of the model and of the mathematical equations that describe its behaviour are well suited for the understanding of almost all the actual circuits and not unfrequently even allow a better design of them.

## Mathematical descriptions

[edit | edit source]Block diagrams can be used to describe a physical system, or its schematic diagram can be used, or the set of mathematical equations characterizing its parts.

However mathematical models, in the form of systems equations, are needed when detailed relationships are required.

Every control system may theoretically be characterized by mathematical equations.

The solution of these equations represents the system’s behavior.

Often this solution is difficult if not impossible to find.

In these cases, certain simplifying assumptions must be made in the mathematical description.

### Linear models

[edit | edit source]*(Applicable to "small signal" conditions - linear equations and formulae - s and jω functions)*

For a large number of control systems those approximations and simplifications lead to systems that can be described by linear ordinary differential equations. Techniques for solving these equations are well documented in the literature of mathematics and engineering.

More precisely, in a large subset of its field of operation, the PLL fulfills certain conditions: it is linear, time invariant, causal, sometimes altogether abbreviated into LTI.

Under these conditions the model is simplified:

- the differential equations become algebraic polynomial equations in the transformed domain.
- all solutions in the t domain are functions = 0 for all t < = 0,
- if the system is in steady state, the Laplace transform (functions of
*s*) overlaps exactly the corresponding Fourier transform. It is enough to substitute*s*with*0 + jω*in the former to obtain the latter.

- In this book, the basic notions of the
**Laplace Transform**are used to analyze of the circuits presented, identify poles and zeros etc. - For
**steady state**phenomena (jitter transfer, jitter tolerance, noise shaping), the analysis is still made in the transformed domain, using the simpler Fourier Transform (obtained for s = 0 + jω)

*Jitter transfer function: the ratio of the output jitter to the input jitter (= the closed loop transfer function).*

*The independent variable ω is the angular frequency of the sinusoidal jitter of the timing transitions*.

- The simplification consists in the use of a real function of a real variable, the
**magnitude of the function**of interest:

1. Real independent variable. In steady state not all possible values of*s*are to be considered, but just those of its imaginary part ω, that is a__real__variable. The function of ω that is obtained still assumes complex values, like magnitude and argument or real and imaginary parts.

2. Real dependent variable. If the system is a minimum phase system (a reasonable assumption), just the(= absolute value) of the system frequency response shall be used, as it contains all the information.*magnitude*

The magnitude is normally represented in a Bode magnitude plot. The argument is often neglected by the PLL engineers.

- The simplification consists in the use of a real function of a real variable, the

- For
**transient**phenomena, the functions in the Laplace domain are reverse transformed to obtain solutions in the form of time function (in this book, mostly the (Unit) Step Response).

In modern communication systems the implementation of the clock and data recovery circuits (CDR) is primarily digital, and the circuits can be very complex (in particular the loop filters and the local oscillator).

The designer sometimes may find it difficult to choose the right architecture and also to understand, in some conditions, the operation of the circuit itself.

Downstream in the product development, the engineers in charge of verification, validation, characterization and testing often do not even attempt to identify the fundamental architecture of the loop.

The best way to solve this is to choose a system architecture that corresponds to the structure of a well understood model of CDR, and to refer to its mathematical description to understand the closed loop operation in all conditions and to actually design the system circuitry blocks.

Reference to the fundamental structure and to the linear modeling that can be applied will also make easier and more effective the subsequent engineering tasks of industrialization, operation and maintenance.

The three model architectures of first order, type 1, and of second order, type 1 and 2, offer the best compromises between stability and performance for practical CDRs.

They can also be well described mathematically and their operation can be easily understood.

Once familiar with their operation, the circuit designer will be able to decide what circuit choices to make, in terms of structure of the blocks and even of the order of its CDR.

**Linear models of the circuit blocks → linear model of the whole circuit**

Each circuit block can be described by a linear model in a certain range of the input signal as long as its parameters remain constant.

When -as is often the case in CDRs – the blocks are designed to operate with linear relation of input to output, the whole systems can be described by a linear model in a wide range of operation.

This book presents in detail three linear models, for the case where both the phase comparator block (based on a sawtooth and linear between the points of jumps to the previous and the next tooth) and the VCO (based on a frequency controlled oscillator with a continuos control and linear within the frequency extremes of the control range) can be described by a linear model.

The three models belong to the two fundamental architectures:

**Non linearities of some circuit blocks prevent their modeling → resort to the linear model of the architecture is still useful**

The usefulness of a linear model certainly applies to a system whose blocks can be individually modeled with linear equations.

But the usefulness of "linear" models extends beyond the study of the linear circuits they are meant to describe.

Even if for one or more blocks a linear model is not possible, the “linear” model of the whole structure can still be useful.

In many practical cases constraints of available technology or of cost prevent the use of “linear” phase comparators and/or of “linear” VCOs.

A non linear system (like a PLL based on a bang-bang phase detector) can be investigated using a linear model, with the restriction that the linear model is only useful in a limited range of the input signal variations.

It is necessary that the system is restricted to a "small signal" condition, where the hard non-linearities do not make the system deviate too much from linearity.

Modeling of these blocks with linear equations is therefore limited only to very small variations of the signal close to the operating point. The parameters of the block(s) can be considered constant as long as the signal moves very liitle around the operating point.

Still the linear models of the “linear” case are useful (apart from being the only closed form tool available!).

__The familiarity acquired with the model of the “linear” architecture can be very helpful to understand how the “non linear” circuit behaves in the neighborhood of a certain operating point__.

When the signal excursions are large and the non linear aspects cannot be neglected, the linear models are no longer valid but simulations are stiil a valid tool left to the engineer.

### Simulators can include some non-linearities

[edit | edit source]*(Applicable to "large signal" conditions, simulations are to be recomputed case by case)*

Parts of this section are based on materials from: Wikipedia/Computer simulation. |

The formal modeling of systems is based on a mathematical model, which attempts to find analytical solutions enabling the prediction of the behaviour of the system from a set of parameters and initial conditions.

When the signals are large, the non-linearities of the circuit blocks can not be neglected and linear models are no longer accurate.

**Computer simulation** is then used as an adjunct to, or substitution for, mathematical models in the system conditions for which simple closed form analytic solutions are not any more accurate, for instance when some hard non-linearities are essential to make a prediction.

- This is typically the case of the acquisition phase of a CDR.

*Some modelling and simulation programs have been developed to verify the content of this book.**In particular some have been developed to make a good prediction of the acquisition phase of a 1st or 2nd order CDR.**Others generate Bode plots of jitter functions of the angular frequency ω.**Each of them includes as output a time and/or a frequency diagram, that have often been used as figures in this book.*

*They are all based on simple calculation sheets, written with free software programs (Apache Open Office and/or LibreOffice), and are available to the reader as free software pieces.*

## Just three architectures are of practical use

[edit | edit source]This book will show some possible model architectures for the CDR, and state that the practical choice is made among just three!

In all practical cases, one of those three models is the fundamental tool that gives a good understanding of the CDR operation.

Linear, time-invariant idealizations of the CDR circuits will be be described in detail.

The fundamental cases of:

- a first order loop for the burst-mode CDR (often, but not always, a phase aligner) (1st order type 1)
- a second order loop for the regenerator (slave) CDR (2nd order type 1)
- a second order loop for non linear blocks with widely variable gain (2nd order type 2)

will be presented and emphasized as the only really important models to use (even when some blocks in the actual implementation are non linear).

More details on why loops are identified by order and type are presented in a page a little further on in this book.

Although such idealizations may not perfectly describe our circuit in some specific aspects (non-linearity of some circuit blocks, etc.) they serves to simplify the mathematics, keep us from getting lost in a welter of algebraic quantities, and –most of all- produce results that can be interpreted quite usefully.

Further on in the book, a section called Structures and types of CDRs/Examples does show the characteristic functions of these three models, as well as the characteristic functions of some others.

The other model architectures that are presented in Structures and types of CDRs/Examples are there only for didactic purposes, but are of no practical use for the electronic engineer.

The three fundamental models instead, are further developed in three dedicated chapters :

### First order systems

[edit | edit source]These systems only have one degree of freedom.

In the study of 1st order PLLs the time constant of the pulse response, called τ (tau), is considered.

This time constant τ is exactly the inverse of the loop gain:

_{φ}* G

_{f}* G

_{VCO}= G

and the natural frequency ω_{n1} is defined as 1/τ = G. *(The subscript n means natural, the subscript 1 - optional - means 1st order)*

1st order systems are primarily used where fast acquisition of lock is important.

Fast acquisition means in actuality that τ/T_{p} ranges between 25 and 100, where T_{p} = 1/ f_{p} is the period of each received pulse.

It should be noted that G_{φ} and G_{VCO} are almost always a inevitable consequence of the technology chosen to implement the circuit. The circuit designer shall therefore play mostly with G_{f} to obtain the desired value of τ.

### Second order systems

[edit | edit source]These systems have two degrees of freedom.

In the models of ^{2nd} order PLLs the quantities considered are the damping ratio ζ and the natural angular (undamped) frequency ω_{n2}.

*(the suffix _{2-} is added to ω_{n} simply to remember that this parameter refers to a 2nd order system,*

*the suffixes*

_{21}or_{22}are added to ω_{n}and to ζ simply to remember that the parameter refers to a 2nd order system, either of type 1 or 2. Type 0 is not used for CDR applications)The damping ratio ζ, for the PLL to be of practical use inside a CDR, must be close to 1 (0.7 to 1.3), to ensure that the behavior of the loop is neither under-damped nor over-damped.

Saying that the second order loop has one more degree of freedom than the first order loop is therefore an overstatement.

It is more fair to say that in both cases the time (and frequency) response of the loop are primarily set by the gain G. In the case of the second order loop it is possible to have a slightly higher variability associated with the (limited) range of variation allowed for .

The natural angular frequency ω_{n2} in a 2nd order loop depends:

- on the loop gain (in analogy with the first order loop)
- on the damping ratio ζ
- but also on the type of the loop:

If the frequency ω_{n1} is defined again as 1/G (like in the 1st order loop), the natural frequencies for the 2-1 and 2-2 loops are:

_{n21}= 2 ω

_{n1}ζ

_{21}; ω

_{n22}= ω

_{n1}/ 2 ζ

_{n22}

*e.g. if ω*.

_{n2}= ω_{n1}, then, ζ = ½2nd order loops of type 1 and of type 2 differ substantially from each other and their architectures are used in different applications of CDRs, as the following pages of this book will emphasize.

### Third order systems

[edit | edit source]**Unity Feedback**

- The
**PLL of a CDR**is a**unity feedback system**because the output (the recovered clock) should be as close as possible to the input (the clock embedded in the incoming pulse stream), apart from the rejection of high frequency components of the latter.**Low Pass**

- The corner frequency of the PLL jitter transfer function
*(approximately ω*indicates that lower frequencies of jitter are tracked, while higher input frequencies are not tracked (= rejected). Lower frequencies are supposed to be the ones needed for the acquisition transient and for tracking the jitter and wander inherent in the incoming signal._{nx}where x is the loop order)^{[1]}**Type 1 or 2, only**

- The
**PLL of a CDR**is either a type 1 or a type 2 loop*(Type means the number of poles of the open loop transfer function in the origin, that is, how many times the factor 1/s appears in the open loop transfer function)*. In a loop of either type 1 or of type 2 the average distance between the input and the output phase*(the sampling error)*is either finite or zero.**Compensator**

- The additional singularities (pole and zero) are added together so that the order of the loop is increased, but not its type. They make up a "compensator".

Without loss of generality, any CDR loop of the 3rd order can therefore be modelled as a 2nd order loop with the addition of a pole-zero pair *(including the extreme cases where either the zero or the pole is at ω = 0 or is at ω = ∞ )* in the forward path of the PLL, increasing the complexity of the loop filter.

**3rd order system models of CDRs**(unity feedback)**are**

2nd order loop with an additional pole-zero pair in the forward path.2nd order loop with an additional pole-zero pair in the forward path.

**Lag compensator**

- The compensator must be a low pass ( ω
_{p}< ω_{z}, i.e. a "lag" compensator), as high frequency jitter and noise in the input signal must be more, and not less, rejected.

**Compensation far away from ω**_{n2}

- Not to interfere with the main characteristics of the CDR that is being retrofitted with the compensator, the compensator itself shall make its effect felt at frequencies at least 2 decades away from the ω
_{n2}of the loop being compensated.^{[2]}*For instance, consider that the jitter transfer function should stay very close to a magnitude = 1 up to ω*_{n2}. Below ω_{n2}, the spectrum of the regenerated clock shall replicate with neither selective emphasis nor selective de-emphasis the spectrum of the clock that is to be recovered from the incoming signal.*In the case of regenerator equipment or of clock distribution in the network, this requirement is explicit, and stringent*.^{[3]}^{[4]}

- This is the reason why the 2nd order models still describe the important performances of the loop, and why the possible compensation only compensates marginal performances. But 3rd order models are complex and are not worth the effort of keeping them in mind as such, as the fundamental performances depend on the underlying 2nd order system only.

- The case of the
**lag compensator**that retrofits a 2nd order system and operates**in a higher range of frequencies**is not very complex and**is always pertinent**in actuality. All real systems are limited in their frequency behaviour by high-frequecy poles that -inevitably- come from the limited bandwidth of the circuits involved. In CDRs moreover, at least one first high frequency pole is deliberately added (the low-pass at the output of the phase comparator or of the charge-pump), but at frequencies high enough not to interfere with the desired loop characteristics.

- The case of the
**lag compensator**that retrofits a 2nd order system and operates**in a lower range of frequencies**would in principle be applicable, but**only to 2 - 1 systems**.*It would not improve a 2-2 CDR, that already has, in then open loop transfer function, very high gain at low frequencies.*

Such 2nd order type 1 system would apparently benefit from the compression to much lower values of the steady state (= sampling) error, that results from the added compensator. However, this improved performance only materialises long after the acquisition phase, proportionally to the ratio between the mean frequency of the pole/zero pair of the compensator and ω_{n2}. This is an example of how the compensation of a CDR does not substantially alter the behaviour of the fundamental loop: in fact, the longer settling time would also be associated to a proportional reduction of bandwidth for tracking with the reduced sampling error.

The two fundamental 2nd order models *( that can be made more fitting as 3rd order systems incorporating a compensator )* remain the fundamental tools to keep in mind at all times to understand the important performances of the loop.

3rd order models are seldom used as such, although the simulations often do include the additional poles and/or compensator.

## Notes and External References

[edit | edit source]- ↑ Inherent, meaning: "that could be present in the signal at the remote transmission point"
- ↑
*The frequency range of interest for a regenerator (jitter transfer) around its cut-off frequency is about +/- 2 decades*: G.783-2006 03 Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks; 15.1.3 Jitter and wander transfer, page 246; ... the jitter transfer measurement is made over the frequency range f_{L}to_{fH}. The lower frequency f_{L}is set to f_{C}/100 (where f_{C}is the –3 dB corner frequency), and f_{H}is defined as .. 100*f_{C}… Jitter above f_{H}is generally agreed to be insignificant relative to regenerator jitter accumulation, and low levels of in-spec jitter generation can easily be confused with an out-of-spec jitter transfer measurement when attempting to measure jitter transfer at high input/output attenuation levels (i.e., below –40 dB). The limits set for f_{L}at f_{C}/100 will always include the frequency at which maximum gain peaking occurs, and limiting jitter transfer measurements to frequencies between f_{L}and f_{H}will help limit testing time. - ↑ Maximum gain peaking: 0.1 dB, see ITU-T Rec. G.8251 (09/2010) page 16: Table A.1-1 − Summary of ODUk clock (ODC) types, and page 23: Table A.7-2 – ODCr jitter transfer requirement.
- ↑
Not to have gain peaking in the jitter (= closed loop) transfer function (
*G(s)/(1+G(s))*), the magnitude of the open loop transfer function (*G(s)*, the nominator ) must never be greater than the magnitude of*(1+G(s))*( the denominator ):G(s)Re(*G(jω)*)^{2}+ Im(*G(jω)*)^{2}< ( 1 + Re(*G(jω)*) )^{2}+ Im(*G(jω)*)^{2}Re(*G(jω)*)^{2}< ( 1 +Re(*G(jω)*) )^{2}Re(*G(jω)*)^{2}< 1 + 2Re(*G(jω)*)+ Re(*G(jω)*)^{2}Re(*G(jω)*) > -1/2