Clock and Data Recovery/Introduction

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Timing in serial data transmission[edit]

To transmit digital information over a certain distance, it is necessary to serialise it (just one guiding medium like cable, fiber,etc. but very high bit rates).

The digital information is often encoded for error detection and correction.

The bit stream is transmitted with its clock information.

The resulting signal, during its journey, is affected by noise and by the transfer function of the transmission medium, and undesired corruption of the information content may follow.

At the receiving end, the signal is restored (it is equalised and the noise filtered out) as much as possible.

Then the timing information is extracted, and the bit stream regenerated.

The electronic circuits that accomplish these last functions inside the data receiver are called the Clock and Data Recovery block (= the CDR).

The timing information, i.e. the clock, is essentially carried by the level transitions of the received signal.

The action of recuperating the clock signal from the received signal is inevitably affected by some deterioration: the square wave extracted is not exactly synchronous with the transmit clock.

Data and clock, during their travel together, have been affected by the noise and by the inter-symbol interference and have acquired:

  • some inevitable delay, due to the physical transit time, and to the extraction process,
  • some timing inaccuracy (= phase modulation, called jitter)
  • some errored bits with a (very) low probability, or –in other words- a bit error rate of very low value (e.g. < 10−19)

The jitter can be kept to a minimum with sophisticated clock extraction circuits, but not eliminated.

On the other hand, in the network topology there are always points where signals that had been originated by the same clock and have cumulated different jitters along different transmission paths, must be put together again.

To absorb the jitter differences an elastic buffer (a special type of buffer memory) is used.

Note: a serialised transmission, with clock and data encoded together, becomes necessary when the bit rate and the wavelength at the bit rate frequency become comparable (when different paths travelled by parallel streams different by 25% or more of a wavelength).
For example: at 1 Gbps the wavelength to refer to is:
c/(1 GHz) = 3 * 108 m/s / 109 sec-1 = 30 cm.
Considering that on PCB the speed is 40% lower than in vacuum, the reference distance is 60% of 30 cm, or about 20 cm. As a result, serial encoded transmission @ 1 Gbps becomes preferred when distance differences amongst parallel paths are 5 cm or more.
The delay difference amongst different parallel paths causes bits, that have been sent at the same instant on different paths, to be received in different clock cycles of the clock at the receiving end. To put them back in sync, it is necessary to insert redundant bits inside each path, so that a frame sync can be detected. Then buffer memories on each path will be used to put back in sync all the bits of the parallel paths. Interfaces with this structure have been proposed, and are in use in some systems.
In most practical applications though, the approach of serialising several parallel streams of bits (typically 8), with the multiplication of the clock frequency, has been found preferable to the alternative approach of adding the sync structure on each bit stream at the transmit end and to recover that, with use of buffer memories, at the receive end.

CDRs and PLLs[edit]

This book deals with CDR (Clock and Data Recovery) circuits, but just the PLLs (Phase Locked Loops) that they incorporate are the circuit blocks that are analyzed and studied.

Set diagram of CDRs and PLLs.png

These PLLs are the important part of a CDR (= used for the Clock Recovery, = the CR part of the CDR).

The DR (Data Recovery) part of the CDR is not studied in any depth, and only the PLLs that are fit for the Clock Recovery function are studied here.

PLLs used for other applications, like for instance position detection of mobile objects or identifications of non-modulated signals, are not considered.

In recent years, owing to the explosive growth of mobile phones, a lot of development has been made on PLLs inside frequency synthesizers (they are not CDRs). It may be said that nowadays a very large part of the PLLs implementations are in frequency synthesizers.

What is special in PLLs for CDRs is a direct consequence of the "blending" of information bits with their clock into a unique serial stream of pulses. Often a NRZ transmission of the information bits does the job perfectly. For other transmission channels a different "encoding" of bits and clock may optimise better the overall performances and increase the distance beyond which a regeneration is needed.

In all cases the "blended" serial stream, owing to the essential "impredictability" of the information bits, does not have a spectrum with neat lines at fixed frequencies but is spread out with large lobes; its level transitions do not occur at each of the possible instants but randomly on just part of them. The concept of "transition density" is used in this book to simplify the mathematics. Moreover, these transitions, when they occur, jitter with respect to their ideal positions because of channel distortion and noise.

On the contrary, the signal that a frequency synthesiser locks into, is a regular periodic waveform, with a spectrum close to a strong line with noise sidebands. Its level transitions occur with a 100% density.

What this book is all about (i.e. application-structure correspondence)[edit]

This book intends to provide a good theoretical base for the understanding, the study and the engineering of PLL systems meant for CDR applications.

The PLL of a CDR is a unity feedback system because the output (the recovered clock) should be as close as possible to the input (the clock embedded in the incoming pulse stream), apart from the rejection of high frequency components of the latter.

CDRs that are made up entirely of circuit blocks that behave linearly are well described by the linear mathematical models, i.e. by linear differential equations with time as independent variable and by their Laplace or Fourier transforms.

Any PLL of a CDR can be described by one out of three "control loop structures" (= architectures, in the sense of block diagrams).

They can be identified just by the two numbers of their order and their type. The figure here below identifies the three architectures from their linear models.

PLLs for CDR are unity feedback loops. When all blocks are linear, order and type numbers are enough to identify the loop structure (=block diagram).

The structures implemented in practice with all linear blocks are:

  1. Loops of 1st order and of type 1, for applications of "phase aligners" and of "end points".
  2. Loops of 2nd order and of type 1, for applications of "regenerators"

CDRs with one or more hard non-linearities can not be sufficiently described by linear mathematical models. ( Additional simulations recomputed for each different signal level are needed).

The widespread (and often inevitable) use of essentially non-linear phase comparators (bang-bang) leads to the use of the more tolerant and robust architectures. (The gain of the bang-bang phase detector is not fixed, but varies with the phase difference at its inputs).

Such structures can still be identified by the numbers of order and type of the corresponding linear loops,

When non-linearities of phase detector and/or VCO limit the possible modeling to computer simulations, neither formulae, nor transforms are possible. Just time functions (simulations of transients). It is nonetheless convenient to use the same identification of linear loops.

and are in practice:

  1. Loops of 1st order and of type 1 (exactly as in 1.1.), for applications of "phase aligners" and of "end points".
  2. Loops of 2nd order and of type 2 (if a linear phase comparator is used this structure is non-preferred) for applications of "regenerators" and of "end points". A detailed analysis of a linear (2.2) architecture (with all linear blocks) is still very important for the comprehension of its practical applications with a bang-bang phase detector.
In the engineering practice of CDRs, just three structures are of practical use. Any other architecture is of interest only in a theoretical sense, because it is not used in the implementation of practical circuits. The three important structures are shown along with their preferred applications

In the book, for all the listed cases (1.1., 1.2. and 2.2.):

  1. the linear model (functions of the complex variable or of , and of the real variable ) is provided, so that the operation in "small signal" conditions can be studied (jitter tolerance, jitter transfer, noise transfer, unit step response, etc.)
    1. of each PLL block and
    2. of the overall system
  2. Important points, where the linear model applicability is exceeded, are investigated, using results obtained trough numerical simulation.
Several versions of simulation programs have been developed and can be provided on request [1] .


  1. Requests can be mailed to: . The simulation programs accept as inputs the loop parameters and the input signal characteristics and provide as output a representation of the "large signal" behavior in those conditions, e.g. of the loop acquisition waveform