Clock and Data Recovery/Miscellanea
Contents
Unit step responses from the (jitter) transfer functions[edit]
The unit step response can be obtained from the (jitter) transfer function as follows:
 take the (jitter) transfer function that is in the s domain (maybe using r in lieu of s/ω_{n} to simplify the notation, i.e. scaling ω_{n} to 1 ) : its reverse transform (that is a function of t) is the unit impulse response. (The transform of the unit impulse is just a constant 1 in the s domain.)
 multiply the (jitter) transfer function by the transform of the unit step function, that is 1/s
 inversetransform into the time domain, i.e. obtain the USR. (Note: when the change of scale property f(s/a) → a*F(t*a) is used, it does not apply to the factor 1/s coming from the unit step, because the step is a unit step!)
The three cases are plotted together here below, using parameter values primarily to allow a meaningful comparison.
It should be emphasized that the value of ζ used for the second order loops in this figure is lower than the values used in practice.
Architectures of just order 1 and 2? Not by chance![edit]
There are just two orders of CDR architectures that are used in actuality.
They can be identified by the order of their jitter transfer functions:
 first order, for the phase aligner CDR, (that was introduced at the beginning of the book);
 second order, for both the possible types 1 and 2, (that were also introduced in the same page).
This “a posteriori” result can be associated elegantly with an “a priori” mathematical theory.
It is known that any possible transfer function can be well approximated by a rational function of the complex frequency “s” (i.e. by the ratio of two polynomials in s).
A rational function in turn can be represented by a partial fraction expansion:
which –in simpler terms means that a CDR can be made with a first order loop, or with a second order loop, or with a product/sum of them.
Common engineering sense dictates that a design be “as simple as it can be made”.
Therefore just one of the simplest possibilities will be chosen:
 a constant is a flat jitter transfer function, and not a real choice;
 a first order (jitter) transfer function will be the choice when the prime considerations are a simple implementation, a quick response (=acquisition) and a high resilience to parameter drifts and nonlinearities;
 a second order (jitter) transfer function will be the choice when either the low frequency performances (steady state error = d.c. phase error ; rejection of low frequency generated noise; ..) or the high frequency performances (tight bandwidth for input jitter filtering) are prime concerns. The 2.2 will be selected in the first case, the 21 in the second.
 any other (inevitably more complex) possibility does not offer much more performances while it makes the circuit more sensitive (often too sensitive) to parameter variations and to small nonlinearities.
The three fundamental models are further developed in three dedicated chapters :
PLL Simulations[edit]
What they are[edit]
Some modelling and simulation programs have been developed to verify the content of this book. Each of them includes as output a time and/or a frequency diagram, that have been used as figures in this book. They based on simple calculation sheets, that have been written with free software programs for calculation sheets (Apache Open Office and/or LibreOffice), and are available to the reader as free software pieces.
Some of these calculation files (the earliest) can be found and downloaded clicking on:
They run on any standard PC.
 The first in the list simulates the signals inside a PLL circuit based on a linear phase detector.
 The second in the list simulates the signals inside a PLL circuit based on a bangbang phase detector.
 The third in the list models the magnitudes of the jω functions of the small signal linear model of the circuits simulated in the first program in the list.
Each of the three programs covers the three main topologies of a PLL: 1^{st} order (type 1), 2^{nd} order type 1 and 2^{nd} order type 2.
Later and more specialised versions (like the ones used for most of the time and frequency diagrams in the book) can be provided on request^{[5]}.
Purpose[edit]
Didactic, to:
 identify and point out the fundamental blocks of the PLL, and consequently of the clock recovery part of the CDR.
 Each block is identified in its function, its input/output connections, its characteristic and its main limitations (= its inevitable nonlinearities).
 The simulated structure is the complete structure of a PLL.
 understand the overall PLL (= clock recovery) operation.
 get familiar with the formulas and equations that constitute the mathematical model (and with their implementation in the simulator or modeling calculation sheets).
 introduce the concept of discrete time, as actual PLLs are often made with digital, discretetime circuitry. In fact this tool:


 only uses 1500 or 3000 time or frequency steps,
 uses difference equations in form of recurrence relations. See also: Difference_equations for the formulae used in the simulation of the loop filter and of the VCO.


How they are made[edit]
Each file includes some description sheets that give a lot of details on how the software is constructed.
These details help understand and even modify the calculation sheets.
The reader is invited to take advantage of those pages as much as of those that do the actual computations.
Each block simulated follows the description that can be found inside this book, that is repeated and furter detailed in the explanation sheets of each software piece.
Limitations[edit]
These programs are simple tools and are correspondingly limited.
Necessary cautions are related to:

 The period of the received line pulses does not coincide with the time step used in the simulations. The latter is in most of the possible cases significantly longer.
 The only frequencies that appear are the frequencies that characterize the loop operation. They are the only ones that are really simulated or plotted.
 The line frequency shall always be for the cases you want to simulate  significantly higher (typically 10 or more times higher) than any frequency significant for the loop operation.
 The programs only use either 1500 or 3000 time or frequency steps.
 A PLL is simulated, not an entire CDR. The simulator will show events like :
 stuttering of the phase error as the input sinusoidal variations (that represent mostly the intersymbol interference jitter) trick the phase comparator back and forth across the tooth edges of the sawtooth characteristic;
 clock slips, that are easily detected when the PLL ends tracking a signal parallel to the input signal, but with a gap that is multiple of the comparator range.
 The simulator programs will not be able to show:
 bit errors, because the simulations do not consider the input bit stream, but only its phase;
 loop gain variations (consequence of variable input transition density, or of non linear gain of the phase detector). This is because of the same reason already mentioned for the point above.
 Some time simulations investigate the acquisition phase of PLLs with nonlinear phase and phase/frequency detectors.
 The period of the received line pulses does not coincide with the time step used in the simulations. The latter is in most of the possible cases significantly longer.
See: The CDR phase comparator and the following pages for more considerations and for time diagrams generated with these simulators.
Burstmode upstream: 20 to 50 transitions for locking into an incoming burst. Case of the 2.5 Gbps US/ 1.25 Gbps DS GPON[edit]
http://www.itu.int/rec/TRECG.984.2/en ITUT Rec. G.984.2
 The example of GPON is more significant than EPON could be, because:
 GPON specs are more demanding in the burst acquisition phase, and
 GPON specifications define the fastest burstmode receiver (in acquisition) that be still good in locked state performances, at the frequencies of the optical access applications.
Physical Layer Overhead[edit]
 In the GPON defined with 2.5 Gbps downstream and 1.25 Gbps upstream, the upstream burst is allowed as many as 96 bits for the socalled Physical Layer Overhead (Plo).
 These bits are meant to allow for the detection of the burst appearance, for the phase lock of the CDR circuit and for the precise identification of the beginning of the reception of information bits of the burst (= burst delimiting function).
Allocation of the bits of the Plo to the OLT functions[edit]
 The first 32 bit times of the 96 are allocated to generate the guard time between bursts.
 16 of the 32 are allocated to mask the transient of extinction of the remote transmitter of the previous burst.
 The following 16 are allocated to give margin against the transient of activation of the remote transmitter that takes over and sends the new burst.
 16 of the 32 are allocated to mask the transient of extinction of the remote transmitter of the previous burst.
 The last 20 bits of the 96 are used for the burst delimiting function.
 During the intermediate 44 bits of the 96, the remote transmitter in the ONT sends a preamble pattern that provides maximal transition density for fast level and clock recovery functions.
 Depending on implementation choices the OLT receiver may be allowed as many as 50 transitions since the start of the burst (p1=0, p2=0, p3= 10 repeated 22 times, plus some initial pulses of the delimiter), or as little as 20 transitions, to achieve lock. The figure that follows shows an actual possible transient in the latter case.
Notes[edit]
 ↑ Using the properties of the inverse Laplace transform:


 , and


 ↑ the factor: can be inversetransformed using:
, where: r = , and the change of scale property:
→  ↑
 ↑ the factor: can be inversetransformed using:
, where: r = and the change of scale property: → can then be used to obtain:
 ↑ Mailing the request to: plz.pllsmltor.file@gmail.com