Clock and Data Recovery/Miscellanea
Contents
Unit step responses from the (jitter) transfer functions[edit]
The unit step response can be obtained from the (jitter) transfer function as follows:
 take the (jitter) transfer function that is in the s domain (maybe using r in lieu of s/ω_{n} to simplify the notation, i.e. scaling ω_{n} to 1 ) : its reverse transform (that is a function of t) is the unit impulse response. (The transform of the unit impulse is just a constant 1 in the s domain.)
 multiply the (jitter) transfer function by the transform of the unit step function, that is 1/s
 inversetransform into the time domain, i.e. obtain the USR. (Note: when the change of scale property f(s/a) → a*F(t*a) is used, it does not apply to the factor 1/s coming from the unit step, because the step is a unit step!)
, and by:
is:the factor: can be inversetransformed using:
, where: r = ,
and the change of scale property: →the factor: can be inversetransformed using:
, where: r = ,
and the change of scale property: →
to obtain:
The three cases are plotted together here below, using parameter values primarily to allow a meaningful comparison.
It should be emphasized that the value of ζ used for the second order loops in this figure is lower than the values used in practice.
Architectures of just order 1 and 2? Not by chance![edit]
There are just two orders of CDR architectures that are used in actuality.
They can be identified by the order of their jitter transfer functions:
 first order, for the phase aligner CDR, (that was introduced at the beginning of the book as:)
 second order, for both the possible types 1 and 2, (that were also introduced in the same page).
This “a posteriori” result can be associated elegantly with an “a priori” mathematical theory.
It is known that any possible transfer function can be well approximated by a rational function of the complex frequency “s” (i.e. by the ratio of two polynomials in s).
A rational function in turn can be represented by a partial fraction expansion:
which –in simpler terms means that a CDR can be made with a first order loop, or with a second order loop, or with a product/sum of them.
Common engineering sense dictates that a design be “as simple as it can be made”.
Therefore just one of the simplest possibilities will be chosen:
 a constant is a flat jitter transfer function, and not a real choice;
 a first order (jitter) transfer function will be the choice when the prime considerations are a simple implementation, a quick response (=acquisition) and a high resilience to parameter drifts and nonlinearities;
 a second order (jitter) transfer function will be the choice when either the low frequency performances (steady state error = d.c. phase error ; rejection of low frequency generated noise; ..) or the high frequency performances (tight bandwidth for input jitter filtering) are prime concerns. The 2.2 will be selected in the first case, the 21 in the second.
 any other (inevitably more complex) possibility does not offer much more performances while it makes the circuit more sensitive (often too sensitive) to parameter variations and to small nonlinearities.
The three fundamental models are further developed in three dedicated chapters :
PLL Simulator[edit]
What they are[edit]
These modeling and simulation programs are free software pieces based on a simple calculation sheet generated with Open Office (free software as well); the calculation files can be found and downloaded clicking on:
They run on any standard PC and simulate the acquisition phase of a PLL inside a CDR circuit.
 The first in the list simulates the signals inside a PLL circuit based on a linear phase detector.
 The second in the list simulates the signals inside a PLL circuit based on a bangbang phase detector.
 The third in the list models the magnitudes of the jω functions of the small signal linear model of the circuits simulated in the first program in the list.
Each of the three programs covers the three main topologies of a PLL: 1^{st} order (type 1), 2^{nd} order type 1 and 2^{nd} order type 2.
Hardware platform[edit]
It has been developed on a Dell Studio 1555, with Intel® Core2® Duo CPU @2.20 GHz, 4.0 GB RAM, Microsoft Windows 7 Home Premium.
Software platform[edit]
This simulator file has been developed with: OpenOffice.org Calc
OpenOffice.org is a free open software that can be downloaded from www.openoffice.org
Purpose[edit]
Didactic, to:
 identify and point out the fundamental blocks of the PLL, and consequently of the clock recovery part of the CDR.
 Each block is identified in its function, its input/output connections, its characteristic and its main limitations (= its inevitable nonlinearities).
 The simulated structure is the complete structure of a 2nd order PLL.
 The filter is the full feature 1^{st} order filter, represented as a block of flat gain G_{f}, followed by a single pole at ω_{f}.
 understand the overall PLL (= clock recovery) operation.
 get familiar with the formulas and equations that constitute the mathematical model (and with their implementation in the simulator or modeling calcsheets).
 introduce the concept of discrete time, as actual PLLs are often made with digital, discretetime circuitry. In fact this tool:


 only uses 1500 time or frequency steps,
 uses difference equations in form of recurrence relations. See also: Difference_equations for the formulas used in the simulation of the loop filter and of the VCO.


Previous versions[edit]
An early version of this simulator (Rev. 1.x) used only:
 Values of ω_{n2}, ζ , or G and τ_{f}, very close to 1. In fact, all values were “normalised”. This avoided the scaling burden to the software, but requested a corresponding effort to the user.
 The loop filter was represented as an true analog circuit, made of an operational amplifier, two resistors and one capacitor. Input values were the values of the resistors and capacitor in the filter circuit.
 A single page to input data and to picture the corresponding acquisition waveforms as well as the filter and jitter transfer functions.
A later version of this simulator (Rev. 2.x) used :
 Automatic scaling of xaxis (frequencies or times) and of yaxis (phases, voltages or magnitudes).
 Coverage of only the 2nd order type 1 topology of PLL.
 No added bias at the VCO input to simulate the difference between line frequency and oscillator free running frequency ( that was introduced only in the 2011 versions).
 A separate sheet (Input data) to input data and others to picture the corresponding acquisition waveform as well as the filter and jitter transfer function.
 Acquisition and magnitude functions in the same file.
How they are made[edit]
Each file includes some description sheets that give a lot of details on how the software is constructed, so that it becomes easy to understand and even to modify.
The reader is invited to take advantage of those pages as much as of those that do the actual computations.
Each block simulated follows the description that can be found inside this book, that is repeated and furter detailed in the explanation sheets of each software piece.
Limitations[edit]
These programs are simple tools and are correspondingly limited.
Necessary cautions are related to:

 The period of the received line pulses does not coincide with the time step used in the simulations. The latter is in most of the possible cases significantly longer.
 The only frequencies that appear are the frequencies that characterize the loop operation. They are the only ones that are really simulated or plotted.
 The line frequency shall always be for the cases you want to simulate  significantly higher (typically 20 or more times higher) than any frequency significant for the loop operation.
 The programs only use 1500 time or frequency steps.
 A PLL is simulated, not an entire CDR. The simulator will show events like :
 stuttering of the phase error as the input sinusoidal variations (that represent mostly the intersymbol interference jitter) trick the phase comparator back and forth across the tooth edges of the sawtooth characteristic;
 clock slips, that are easily detected when the PLL ends tracking a signal parallel to the input signal, but with a gap that is multiple of the comparator range.
 The simulator programs will not be able to show:
 bit errors, because the simulations do not consider the input bit stream, but only its phase;
 loop gain variations (consequence of variable input transition density, or of non linear gain of the phase detector). This is because of the same reason already mentioned for the point above. See: The CDR phase comparator for more considerations.
 The period of the received line pulses does not coincide with the time step used in the simulations. The latter is in most of the possible cases significantly longer.
Burstmode upstream: 20 to 50 transitions for locking into an incoming burst. Case of the 2.5 Gbps US/ 1.25 Gbps DS GPON[edit]
http://www.itu.int/rec/TRECG.984.2/en ITUT Rec. G.984.2
 The example of GPON is more significant than EPON could be, because:
 GPON specs are more demanding in the burst acquisition phase, and
 GPON specifications define the fastest burstmode receiver (in acquisition) that be still good in locked state performances, at the frequencies of the optical access applications.
Physical Layer Overhead[edit]
 In the GPON defined with 2.5 Gbps downstream and 1.25 Gbps upstream, the upstream burst is allowed as many as 96 bits for the socalled Physical Layer Overhead (Plo).
 These bits are meant to allow for the detection of the burst appearance, for the phase lock of the CDR circuit and for the precise identification of the beginning of the reception of information bits of the burst (= burst delimiting function).
Allocation of the bits of the Plo to the OLT functions[edit]
 The first 32 bit times of the 96 are allocated to generate the guard time between bursts.
 16 of the 32 are allocated to mask the transient of extinction of the remote transmitter of the previous burst.
 The following 16 are allocated to give margin against the transient of activation of the remote transmitter that takes over and sends the new burst.
 16 of the 32 are allocated to mask the transient of extinction of the remote transmitter of the previous burst.
 The last 20 bits of the 96 are used for the burst delimiting function.
 During the intermediate 44 bits of the 96, the remote transmitter in the ONT sends a preamble pattern that provides maximal transition density for fast level and clock recovery functions.
 Depending on implementation choices the OLT receiver may be allowed as many as 50 transitions since the start of the burst (p1=0, p2=0, p3= 10 repeated 22 times, plus some initial pulses of the delimiter), or as little as 20 transitions, to achieve lock. The figure that follows shows an actual possible transient in the latter case.