Clock and Data Recovery/Structures and types of CDRs/The (slave) CDR based on a second order PLL/2nd order type 2
Generalities of the 2^{nd} order type 2 PLL[edit]
Robust, tolerant but excitable. Zero phase error once locked, to sample the received eye exactly in the middle  independently of the loop gain.
The CDRs are unity feedback systems and – in most cases of type 1.
When the loop gain cannot be known (because of a bangbang phase detector or because of a highly variable transition density in the received signal), the type 1 architectures may not be adequate.
The PLL designer, faced with a loop gain that can vary in a very large interval, may be unable to design so that the sampling error remains negligible in all conditions.
The steady state error of the type 1 CDRs, both 1st and 2nd order, as seen earlier, is:
that represents how much the sampling instant deviates from the middle point of the received pulses.
E_{s} depends on the accuracy of the VCO, (ω_{p} ω_{fr}), and on the open loop gain, G.
A type 1 PLL (1^{st} or 2^{nd} order) may be inadequate, if G_{φ} varies in a wide range, for two reasons:
 the VCO accuracy ω_{p} ω_{fr} is too large a percentage of ω_{p}, (which is the case, for example, with onchip RC or LC oscillators where ω_{fr} may vary from sample to sample by more than 20% and be furthermore sensitive to voltage supply and temperature)
 the open loop gain G, product of G_{φ} and G_{f} and G_{VCO}, is too low, (which is sometimes the case, for instance, when the feedback circuit of the oscillator has an especially high Q to be insensitive to certain forms of phase noise, or which is often the case if some hard nonlinearities are present in the loop, making the gain of one of its blocks variable with the signal amplitude, and rendering a linear modelling impossible. This is typically the case is when a bangbang phase detector is used. Conditions of low gain have to be expected, but a general model is not available to cover all such possibilities).
The compression to zero of the steady state error can be obtained in return for, as it will be shown, some reduction of the small signal performances.
This is obtained going from a type 1 to a type 2 loop. (A 1st order type 2 loop can not exist: the 2nd order type 2 loop is the architecture of choice if no sampling error is desired).
The Amplifier/filter (of the loop of 2nd order and of type 2) changes from
a finite pole and one zero at ∞ of the 2nd order type 1 loop, (or from the flat gain of the 1st order type 1 loop),
and now exhibits one pole in the axes origin and one finite zero .
Comparator and VCO models are unchanged.
The compression to zero of the steady state error can be obtained even if the gain of one block is non linear (e.g. when a bangbang phase detector is in place), because of the inherent robustness of this loop.^{[1]}
As it will be shown with a detailed analysis of the "linear" version of the loop, the remarkable caracteristics in the large signal case are accompanied by poor small signal performances.
The following development of the model (the simulations of this 22 loop are also available in the simulator that can be retrieved following the link [link]...) will show that this loop has the main advantages of :
 a zero steady state sampling error (no matter what the loop gain is)
 a very good jitter tolerance at low frequencies
 a very strong rejection of low frequency noise from the VCO
and the disadvantages of:
 a weak jitter filtering rolloff, that means poor rejection of channel noise, and a very high gain peaking.
 a tracking that overshoots when the input phase jumps abruptly
 under damped noise and jitter transfer characteristics around the loop corner frequency
which overall qualify this loop architecture as inadequate for regenerator applications, but good when the large signal performances are important in presence of hard nonlinearities.
In particular, when the phase comparator is of bangbang type and the accuracy of the VCO freerunning frequency f_{fr} is poor, this architecture is preferred for CDRs.^{[1]}
For example, in a field different from CDRs, this architecture is interesting in applications of spatial detection and ranging of a moving target (where large signals are the normal case, and some overshooting of the target is desirable).
In the most classical reference for PLLs ^{[2]}, that dates back to 1966, when CDRs were just one application (the last among the listed !), this architecture, identified as “highgain, second order loop”, was described with the greatest detail and indicated as the most common.
Its robustness and versatility are certainly the reasons for such early succes and present longevity, although it is not preferred today for burstmode or for regenerator applications of CDRs.
ω_{n2} and ζ as functions of G and τ_{z}[edit]
As derived in the figure above, the jitter transfer function of the 22 loop is:
To derive the loop parameters ω_{0} and ζ from the circuit parameters ω_{z} and G, let's contrast the two versions of the jitter transfer function:
Equating the two pairs of significant coefficients of the denominators: = τ_{z} and: ω_{o}ζ = → →
Setting ω_{n2} and ζ  Setting G and τ_{z} 

G = 2ζω_{n2}  ω_{n2}^{2} = G/τ_{z} 
τ_{z} = 2ζ / ω_{n2}  ζ^{2} = Gτ_{z}/4 
ω_{o} = ω_{n2}  ω_{z} = 1/τ_{z} = ω_{n2}/2ζ 
Dimensional check:
G = G_{φ} G_{f} G_{VCO} [rad/sec]
G_{φ} [volt/rad], G_{f} [volt/volt], G_{VCO} [rad /(secvolt)]
ω_{n2}^{2} = G/τ_{z} [sec2]
ζ = √Gτ_{z}/2 [ adimensional ]
jω and t functions[edit]
Jitter transfer function[edit]
The characteristic equation is: a(s) = 0 , where a(s) = s^{2}+ 2ζω_{n2}s + ω_{n2}^{2}= 0 .
The poles p_{1} and p_{2} are the roots of a(s):
Its magnitude is:
The high frequency rolloff of the jitter transfer function of this 2^{nd} order type 2 loop is a single pole low pass (20 dB/decade) like the 1^{st} order type 1 loop, instead of a double pole low pass (40 dB/decade) of the 2^{nd} order type 1 PLL^{[1]}.
ω_{z} = ω_{n2} /2ζ
If ω_{z} << ω_{n2} (i.e. when ζ >>1), the loop behaves very much like a slow first order, type 1 loop with the additional, elimination of the steady state error (of the type 1 loop).
This can be understood considering that
 the first pole at ω_{n2}(1√(ζ^{2}1)) ≈ 2ω_{z} compensates the zero at ω_{z} and that
 the second pole is at a frequency much larger than ω_{n2}, that is at ω_{n2}(1+√(ζ^{2}1)) ≈ ω_{n2}ζ.
If instead ω_{z} has been designed to be greater than ω_{n2} /2 , then ζ becomes smaller and smaller (ζ = ω_{n2} /2ω_{z} ) and the loop becomes underdamped at frequencies close to ω_{n2} /2. Overshoots at the otput of the filter will appear. In this condition, the non linearity (the saturation boundaries) of the node between filter and VCO will be reached very often. This clamping at the saturation boundaries may be seen as a “reduction of the underdamping”, and may be inevitable (and therefore accepted) in loops with very narrow tuning range of the VCO.
The optimum would be in the interval 0.7 < ω_{n2}/2ω_{z} <1.3.

 But this circuit architecture is often used with bangbang phase detectors whose gain Gφ varies with the signal amplitude, and is maximum at the smallest signal amplitude (= when the phase jitter is minimum that is when acquisition is almost or fully achieved).
 In that case the loop behaviour is (approximately!) like a linear overdamped loop (ζ = Gτ_{z}/4 where G is much larger because G_{φ}, although variable with the error signal, is much larger than in the linear model).
Error signal[edit]
The magnitude of the ratio error/input, i.e. of the normalized errorsignal function, is:
zero in ω_{z}
poles in  ζω_{n2} ∓ ω_{n2} √ζ²  1
Jitter tolerance[edit]
The normalized jitter tolerance can be obtained
as X(jω)_{Ε(jω) = 1} that is:
The asintote towards low frequencies (in the loglog plot) has a slope of 40 dB/ decade (as opposite to the slope of 20 dB/ decade of the type 1 systems).
This is typical of all type 2 systems, that are more tolerant ( 20 dB/ decade more) of low frequency jitter than type 1 systems.
The rejection of generated (VCO) noise…..[edit]
Noise injected into the different nodes of the PLL loop reaches the output modified by the loop operation.
See also the page Clock and Data Recovery/Noise is shaped by the PLL structure.
The description in the s domain of such modifications for a 2^{nd} order type 2 PLL is:
The noise generated by the filter N_{f} is modified by the transfer equation TF_{Nf} = (TF_{VCO}) / 1 + TF_{PhComp}*TF_{filter}_{*}TF_{VCO})
The noise generated by the VCO N_{o} is modified by the transfer equation TF_{No} = 1/(1 + TF_{PhComp}*TF_{filter}_{*}TF_{VCO})
Y(s) = X(s) * ((G_{φ} G_{f} G_{VCO})((sτ_{z} + 1 )/τ_{z}s^{2})) / (1 + (G_{φ} G_{f} G_{VCO})((sτ_{z} + 1 )/τ_{z}s^{2}))
 + N_{φ}(s) * (G_{f} G_{VCO})/((sτ_{z} + 1 )/τ_{z}s^{2}) / (1 + (G_{φ} G_{f} G_{VCO})((sτ_{z} + 1 )/τ_{z}s^{2}))
 + N_{f}(s) * (G_{VCO}/s) / (1 + (G_{φ} G_{f} G_{VCO})((sτ_{z} + 1 )/τ_{z}s^{2}))
 + N_{o}(s) * 1 / (1 + (G_{φ} G_{f} G_{VCO})((sτ_{z} + 1 )/τ_{z}s^{2}))
Y(s)/N_{o}(s) = s^{2}τ_{z} / ( s^{2}τz + (Gφ Gf GVCO)((sτz + 1 ))
Y(s)/N_{o}(s) = s^{2}τ_{z} / ( s^{2}τ_{z} + Gsτ_{z} + G )
two zeros in the origin and two poles at: − ( G + √( G^{2}− 4G/τ_{z} ) ) / 2 ; − ( G − √( G^{2}− 4G/τ_{z} ) ) / 2
Its magnitude is: Y(jω)/N_{o}(jω) = 20log10((ω^{2}τ_{z})/(ω^{2}τ_{z}^{2}G^{2}+(Gω^{2}τ_{z} )^{2})^{1/2})
A 2  2 loop attenuates the VCO noise at all frequencies below , with a double slope (40 dB/decade).
There can be noise amplification at certain frequencies because of the gain magnitude oveshoots 0 dB, whenever <√1/2 .
The peaking of the overshoot occurs at ω = ω_{22} / √1 − 2ζ², and reaches as high as 20log_{10}(1 / (2ζ√1 − 2ζ²)).

 The 22 loop is a good choice if a noisy VCO must be used and is certainly preferable when some loop parameters can vary in a wide range because of hard non linearities (if G can become very large in certain conditions e.g. when a bangbang detector is used)).
This architecture is the best of the three to mitigate a noisy VCO (see the double slope of attenuation for low frequencies), but the damping ratio shall remain larger than √1/2 = 0.707, to avoid amplification of noise frequencies around ω_{22}.
Unit Step Response[edit]
The analysis in the frequency domain (jitter transfer, error function, jitter tolerance, noise transfer) models the circuit behavior in the "small signal" conditions.
The Unit Step Response is part of the same mathematical model, and gives a time domain perspective of the circuit,
that complements the frequency domain perspective offered by the jω functions.
The Unit Step Response can be obtained from the jitter transfer function, multiplying it by 1/s and inverse transforming.
In fact the (unit) step response shows the response of the PLL output phase to an abrupt variation of the input phase.
The (unit) step response is used primarily to see how the acquisition phase evolves towards phase lock.
The step response of this type of loop is fast because the loop filter does not attenuate the high frequencies, (like in the case of the 1^{st} order loop, and unlike the case of the 2^{nd} order type 1 loop).
The output phase overshoots significantly (it does so even for ζ ≥ 1) the input (that is a unit step starting at t = 0).
The overshoot with ζ ≥ 1 is a consequence of the amplification of the low frequencies and of the infinite gain at d.c. in the loop filter.
The area of the step response above the asymptote compensates exactly for the area below.
It is however important to be cautious when using the step response to model the system in case of large abrupt variations of the input phase.
Care is necessary because the boundaries of linear operation of the system (the range of the phase comparator, the swing of the filter output, the control range of the VCO, ..) can easily be reached and exceeded during a (relatively) large transient.
The CDR will very likely still operate correctly but its performances may not be well described by this linear model during such transient.
The response when left freerunning[edit]
The CDR is left freerunning, for instance, when the incoming signal has no level transitions ( and consequently the phase comparator cannot detect its phase ) .
At that moment the phase comparator can only output its neutral  i.e. no phase difference  level.
 In a 1^{st} order loop, the comparator output waveform is applied directly to the VCO input (apart from a possible flat amplification).

 The VCO abruptly changes its frequency (that was f_{p} as long as it was in lock) jumping to its freerunning frequency f_{fr}.
 The sampling point (its phase is the integral of the VCO frequency step) drifts from its lockin point following a linear (phase) ramp.
 The slope of the ramp is the frequency difference between the freerunning frequency of the local oscillator and the frequency of the remote transmit oscillator:

 The (1^{st} order type 1) loop drifts 1 rad exactly after a time equal to: f_{p} / f_{p} – f_{fr} periods of received pulses.
 In a 2^{nd} order type 1 loop, the loop filter smooths down the frequency step. The phase ramp does not start immediately, but smoothly. The smoothing corresponds to the time constant of its filter, τ_{f}.
 In a 2^{nd} order type 2 loop, as long as correct lock is maintained, the comparator output signal is about zero. The filter that follows, with its practically infinite gain at d.c., is able to provide exactly the "drive error" (that corrects the VCO from f_{fr} to f_{p}) with a negligible signal level at its input.
When transitions disappear, the comparator output does not show any (big) change: zero it was and zero it becomes.
But the infinite d.c. gain, in this open loop condition, makes the circuit evolution depend on the small manufacturing imprecisions!
The unit step response of the loop filter is the sum of a unit step plus a ramp of slope 1/τ_{z} , multiplied by G_{f}. But the actual response is generated by a step of height equal to just the output offset of the phase comparator in its neutral state (plus the possible error signal, originated by input jitter, present immediately before), therefore attenuated in proportion with respect to the unit step response!
This offset is originated by manifacturing mismatches between circuit stages that are theoretically identical, and amounts to around one percent of the total signal range, while the step (of the type 1 loops) coming from (f_{p}  f_{fr}) / f_{p} is closer to 20 percent points.
This helps understand the differences in the architectural sense, but in practice each of the three models would be used in a different application, under widely different conditions.
and eventually overtakes the drift of the type 1 loops.
External References[edit]
 ↑ ^{a} ^{b} ^{c} Richard C. Walker (2003). "Designing BangBang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 3445, a chapter appearing in "PhaseLocking in HighPerformance Sytems  From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0471447277. http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf.
 ↑ Floyd M. Gardner (1966). "Phaselock Techniques". John Wiley & Sons Canada, Limited. http://www.abebooks.com/9780471291565/PhaselockTechniquesGardner0471291560/plp.