Clock and Data Recovery/Structures and types of CDRs/Applications of the 2nd order type 1 architecture

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Application of the 2-1 architecture[edit]

This architecture is used in practice for:

  • line regenerators, and for
  • slave clocks in long distance (=Telecom) networks.

The implementation with linear phase comparator and linear VCO is the typical case, as it best fits the target applications.

The linear model in this 2-1 case finds a direct application!

As seen in a previous page, the performance parameters to consider are ωn2 and ζ.

They are related to the design parameters G and τf as follows:

2nd order PLL of type 1: relations between performance and design parameters
 Setting ωn2 and ζ   Setting G and τf 
G = ωn2 / 2ζ ωn22 = G/τf
τf = 1 / 2ζωn2 ζ2 = 1 / 4τfG

τf is the time constant of the added filter and ωf = 1/ τf is its cut off frequency;

G is the open loop DC gain = Gφ * Gf * GVCO.

(It may also be pointed out that the 2 - 1 loop becomes unstable if the natural frequency ωn2 {that normally is about 1/2 ωf or lower} gets close to ωf. As ωn2 grows if the loop gain grows, it is not possible to use a bang-bang detector because its gain varies very much with the phase difference it measures).

The ITU-T Recommendations often indicate as a reference model the 2-1 architecture.

For instance: “a SEC will generally mimic the behavior of a 2-nd order (type 1) linear analogue phase locked loop. This allows the use of the terms (equivalent) 3 dB bandwidth and (equivalent) damping factor, as they are used in analog PLL theory, irrespective of the fact that in the implementation of a SEC, digital and/or non-linear techniques may be used."[1]

( SEC: a SDH equipment slave clock)

In fact, when requirements are the following, like in a telecom networks:

  • continuous transmission mode
  • receiver cost may increase if an increase of the regeneration span offers a larger saving.

These translates into:

  • filtering incoming phase noise is important
  • the cost of a low local noise generation is affordable
  • fast acquisition is not important

then the preferred CDR implementation includes a phase comparator that behaves linearly, a low pass filter and a low noise oscillator whose frequency varies proportionally to the control signal. The PLL behaves as a 2-1 linear loop.

When more CDRs are chained so that their jitter transfer functions combine, then gain peaking must be minimum or absent: ζ >> 0.7.

ζ is larger than 1[edit]

The value of ζ shall be set by design larger than 1 (1.1 to 1.9).

Amplification of jitter may - if the input jitter at those frequencies is large enough to start with - accumulate when more identical regenerators are interconnected in a chain along the signal path (a not infrequent case in geographical networks).
  • When ζ >> 1, the loop behaves more and more like a first order loop. The sharp cutoff at about ωn2 , typical of a good 2nd order loop, smooths out, and the jitter at frequencies around ωn2 is less effectively rejected.
  • Similar indications are derived from the study of the error signal in this 2-1 loop:
  • Large values of ζ ( >> 1) involve a large error even at frequencies much lower than \omega_{n2};
  • small values of ζ ( < 1.0) correspond to large overshoots of the phase error just above ωn2.

The transition Density DT is never stable at its maximum value (100%). Rather, the loop must not become underdamped when DT is somewhat lower than its average of 50%. DT = 33% means a comparator gain reduction of 67% from the Gφ value.

As ζ varies inversely to the square root of G, it must be kept correspondingly larger by design.

Values of ζ between 1.1 and 1.9 are therefore an inevitable design choice. Other considerations that can be drawn from the study of the jitter tolerance function confirm the choice of this range of ζ values for the regenerator CDR design.

ωn2 and ωf[edit]

The cut-off frequency of the loop filter block ωf =1/τf fixes the bandwidth of the closed loop, apart from the minor adjustments of ζ as it varies within its allowed range).

The natural frequency ωn2 (which can also be seen as the jitter cutoff frequency of the CDR) is defined by the loop gain and by ωf :

ωn22 = Gωf

and can also be expressed as a function of just ζ and ωf :

ωn21 = ωf /2ζ21

This simple formula tells that (in a 2nd order PLL of type 1 where ζ21 must remain close to 1) the natural frequency ωn21 remains close to half the cutoff frequency of the loop filter!

VCO good centering and narrow jitter bandwidth

In the 2nd order, type 1, loop, the VCO frequency mismatch fp – ffr becomes a sampling time error Es according to:

Es = (ωp – ωfr)/G

(G= Gφ*Gf*GVCO) For fixed open loop dc gain G and filter time constant τf, the jitter cut-off frequency ωn2 is:

ωn2 = G * 2ζ
Es = ((ωp – ωfr) * 2ζ ) / ωn2

It is easy to see that, for a 1st order type 1 loop: Es = ((ωp – ωfr) / ωn1

The same equation, rearranged, tells that the frequency mismatch and the maximum Es define how tight the the loop jitter bandwidth can be:

Es / 2ζ = (ωp – ωfr) / ωn2 = ((ωp – ωfr)/ωp) / (ωn2p)
n2 / ωp ) = ((ωp – ωfr) /ωp) / (Es /2ζ ))

It is easy to see that, for a 1st order type 1 loop: (ωn1p ) = ((ωp – ωfr) /ωp) / Es )

For instance, if Es is conservatively set as low as = 0.1 rad, then ωn2 can be : ωn2 ≃ 20 * (ωp – ωfr) .

As seen already about CDRs and parts per million of frequency mismatch, the free running frequency of a slave CDR may differ no more than 50 ppm from the frequency of its remote master (very low cost quartz crystal), or 10000 ppm (monolythic RC oscillator after EWS trimming), or even differ less than 1 ppm, still without big cost concerns (quartz for GPS receivers inside mobile phones). Less than 0.1 ppm is typical of professional equipment.

The four mentioned cases set a respective minimum for the design choice of ωn2 at: 0.001 ωp , 0.2 ωp , 2 e-5 ωp , 2 ppm ωp .

ωn21 and ωn1[edit]

In a 1st order loop, the quantity ωn = G tells how fast the loop reacts. The higher ωn, the faster the loop response.

For the 2nd order loop it is difficult to relate ωn2 to how fast the loop reacts to a change. In the 2 - 1 loop, for ζ ≈ 1, and setting -for sake of comparison- the gain G equal for the two loops:

ωn21 = 2ζ21 G
ωn21 ≈ 2 ωn1

In other words a 2nd order type 1 PLL (ζ ≈ 1) wold seem twice as “fast” as a 1st order PLL of the same gain!

But it can also be seen that, setting, for sake of comparison, ωn2 = ωn, then the 2nd order type 1 loop is not practically slower than the 1st order loop!

“Slow or fast” in the sentences above means both:
- slow or fast to acquire the lock condition
- slow or fast to drift to its free running frequency when the input signal disappears.
The following figure contrasts the Unit Step Responses of the 3 important PLL models:
USRs of the 3 important loop models.
2 - 1 and 2 - 2 are plotted for natural undamped frequency = 6.28 Grad/sec and ζ = 1
1 -1 is plotted for both natural frequency = 6.28 Grad/sec and 3.14 Grad/sec.

Note that the USR of the 1 - 1 loop model is plotted for two different values of ωn1: ωn1 = ωn2 of the other two loops and 1/2 ωn1 = ωn2 of the other two loops

External References[edit]

  1. ITU-T G.813 (03/2003) Timing characteristics of SDH equipment slave clocks (SEC), Appendix II: Considerations on bandwidth requirements, noise accumulation and payload wander accumulation, II.1 Introduction.