Clock and Data Recovery/Structures and types of CDRs/Applications of the 2nd order type 1 architecture
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Application of the 21 architecture[edit]
This architecture is used in practice for:
 line regenerators, and for
 slave clocks in long distance (=Telecom) networks.
The implementation with linear phase comparator and linear VCO is the typical case, as it best fits the target applications.

 The linear model in this 21 case finds a direct application!
As seen in a previous page, the performance parameters to consider are ω_{n2} and ζ.
They are related to the design parameters G and τ_{f} as follows:
Setting ω_{n2} and ζ  Setting G and τ_{f} 

G = ω_{n2} / 2ζ  ω_{n2}^{2} = G/τ_{f} 
τ_{f} = 1 / 2ζω_{n2}  ζ^{2} = 1 / 4τ_{f}G 
τ_{f} is the time constant of the added filter and ω_{f} = 1/ τ_{f} is its cut off frequency;
G is the open loop DC gain = G_{φ} * G_{f} * G_{VCO}.
(It may also be pointed out that the 2  1 loop becomes unstable if the natural frequency ω_{n2} {that normally is about 1/2 ω_{f} or lower} gets close to ω_{f}. As ω_{n2} grows when the loop gain grows, it is not possible to use a bangbang detector because its gain varies very much with the phase difference it measures).

 The ITUT Recommendations often indicate as a reference model the 21 architecture.
 For instance:
 “a SEC will generally mimic the behavior of a 2nd order (type 1) linear analogue phase locked loop. This allows the use of the terms (equivalent) 3 dB bandwidth and (equivalent) damping factor, as they are used in analog PLL theory, irrespective of the fact that in the implementation of a SEC, digital and/or nonlinear techniques may be used."^{[1]}
 ( SEC: a SDH equipment slave clock)
In fact, when requirements are the following, like in telecom networks:
 continuous transmission mode
 receiver cost may increase if an increase of the regeneration span offers a larger saving.
they translates into:
 filtering incoming phase noise is important
 the cost of a low local noise generation is affordable
 fast acquisition is not important
then the preferred CDR implementation includes a phase comparator that behaves linearly, a low pass filter and a low noise oscillator whose frequency varies proportionally to the control signal. The PLL behaves as a 21 linear loop.
When more CDRs are chained so that their jitter transfer functions combine, then gain peaking must be minimum or absent: ζ >> 0.7.
ω_{n} and ζ in continuousmode regenerator CDRs[edit]
The ITUT Recommendations (the G.7XX series and the G.8XX series in particular, see for instance the G.825) describe a lot of the characteristics of clock regeneration recommended for applications in continuous mode.
With a little reverse engineering of the large amount of data available from that source (and making reference to the model of a PLL of the 2^{nd} order, type 1), the preferred values that can be obtained are:
The damping coefficient ζ must be  in all conditions  larger than 0.66 in order to keep the maximum jitter amplification (maximum value of the jitter transfer function) below 0.1 dB.
Another aspect that suggests values of ζ larger than at least 0.7, is the overshoot when tracking a sinusoidal jitter. Both the diagram of the jitter tolerance and the diagram of the jitter error show that (for ω_{n2} just above 1) there is an extra deterioration of the tracking performances for low values of ζ (See: 1, 2, 3, 4).
The most important consideration, that forces a substantial margin in the design value chosen for ζ in the CDR design, is however the derating due to the transition density expected in the incoming pulse stream. The transition density generally oscillates around 50%, well below its theoretical maximum of 100%.

 It is always necessary to account for a transition density not larger than 50%, and in some cases (depending on the line code and on the product of the maximum run length duration  about 72 bits^{[2]}^{[3]} times the jitter transfer bandwidth) even lower.
Finally the construction tolerances when actually building the physical CDR circuit are to be considered, along with the variations that may come with aging. They can affect the parameters significantly (sometimes as much as +/ 30%, like in the case of monolithic integrated circuits).
Taking into account all these derating factors, in practice the model parameters of CDRs for continuous mode applications fall inside the following ranges:
Parameter  DT = 100 %  DT = 33 % 

G  G = G_{φ} G_{f} G_{VCO}  0.33 G 
ω_{n}  1/50 to 1/15,000 of ω_{0}  1/90 to 1/26,000 of ω_{0} 
ζ  1.0 to 1.3 (typ. 1.1)  1.8 to 2.3 (typ. 1.9) 

 The extreme cases with ω_{n} < 1/10,000 ω_{0} can only be found in some long distance links on single mode optical fibre, where a high number of regenerators are located in series along the line, each one with its own CDRs.

 In that case the jitter accumulation is the most critical aspect. All the above conditions shall never combine in a worst case that make the jitter amplification of each regenerator exceed +0.1 dB at any frequency, corresponding to ζ equal or lower than 0.652.^{[4]}
 Jitter around that particular frequency of peak amplification could be repeatedly amplified along the line and accumulate enough power to become source of error bits.
 Another ITU reference goes even further and recommends that any peaking of the transfer function gain is to be avoided in long regenerator chains, which means ζ < 0.7.^{[5]} , which is the same as to recommend ζ never to be smaller than 0.7 .
ω_{n2} and ω_{f}[edit]
The cutoff frequency of the loop filter block ω_{f} =1/τ_{f} is the main parameter that sets the bandwidth of the closed loop, apart from the minor adjustments of ζ as it varies within its allowed range.
The natural frequency ω_{n2} (which is the jitter cutoff frequency of the CDR) can also be expressed as a function of the loop gain and of ω_{f} :
or can be expressed as a function of just ζ and ω_{f} :
This simple formula tells that (in a 2^{nd} order PLL of type 1 (where ζ_{21} must remain close to 1) the natural frequency ω_{n21} remains close to half the cutoff frequency of the loop filter!
It has been shown that the VCO ffr accuracy can set a limit to how narrow the jitter bandwidth can be.
External References[edit]
 ↑ ITUT G.813 (03/2003) Timing characteristics of SDH equipment slave clocks (SEC), Appendix II: Considerations on bandwidth requirements, noise accumulation and payload wander accumulation, II.1 Introduction.
 ↑ The maximum runlength that must be tolerated in SDH systems is 72 CID (Consecutive Identical Digits): G.7832006 03 Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks; Appendix V Verification of SDH equipment CID immunity, page 275; 72 bits …
 ↑ G.957200603 Optical interfaces for equipments and systems relating to the synchronous digital hierarchy; Appendix II, Implementation of the Consecutive Identical Digit (CID) immunity measurement
 ↑ ITUT Rec.G.783 (03/2006), in particular Table 152 / G.783  Jitter transfer parameters and 15.1.3 Jitter and wander transfer
 ↑ ITUTRECG.824 Fascicle III.5 Supplement 36 Page 285 Jitter and wander accumulation in digital networks, ... no peaking in the regenerator jitter/wander transfer characteristic, ...