Clock and Data Recovery/Structures and types of CDRs/The CDR Phase and Frequency Detector PFD

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Many practical (slave) clock recovery circuits with a PLL architecture require some type of frequency acquisition aid.

Exceptions are only found where very stable VCOs, such as crystal oscillators, are used to insure that the frequency error is never larger than the natural acquisition range of the PLL ( a range that is close to the PLL closed-loop bandwidth ).

Excluding these stable VCOs, and other acquisition aids, such as frequency sweeping, a frequency discriminator is required as an integral part of any phase-detector for modern monolithic CDRs ([1] pages 259..260 ).


Frequency (comparison and) detection[edit]

A serial stream of NRZ data arriving at a pulse frequency fp is not distinguishable form a stream at 2fp made of pairs of identical pulses, nor from a stream at 3fp made of triplets of identical pulses.

A serial NRZ stream of data can be regenerated with a clock at frequency f, or 2f, or 3f, or higher multiple.#A serial NRZ stream of data can be regenerated with a clock at frequency f, or 2f, or 3f, or higher multiple.

Some additional information about the absolute value of fp is necessary to correctly recover clock and data. Since the uncertainty comes in steps of 100% of fp, an indication of fp with an approximation of +/- 50% is (barely) sufficient.

In practical CDR applications the uncertainty is always contained within ± 25% and in most cases within ±5% (most of this uncertainty comes from the inaccuracy of the VCO free running frequency) . Additional circuitry that can detect the frequency of the incoming data in that range will be adequate, as it will be shown.

In frequency synthesisers the problem of frequency aided acquisition is equally important as in CDRs, but in synthesisers the incoming signal and the local clock are both perfectly periodic waveforms and a phase and frequency detector with a simple architecture can be used [2]. A straight forward comparison of the respective cycle period is possible, and effective. On the other hand, synthesizers often require capture ranges well in excess of +/- 25%.
In CDRs instead, the missing transitions of the incoming signal make the frequency comparison with the local clock a more complex affair.



Need for frequency detection (in addition to phase detection) in CDRs[edit]

A loop filter is inserted between phase comparator and VCO, in CDRs where jitter and noise performances are important (Architectures 2 - 1 and 2 - 2).

Both for architectures 2-1 and 2-2, when high transmission speed is involved, a jitter-out / jitter-in bandwidth of about 1/1000 of the bit rate is specified by most standards [3].

The "jitter-out /jitter-in" bandwidth, called ωn2 in the modeling of these 2nd order loops, is therefore specified and made by design to be around ωp/1000 ( ωp is the angular frequency of the pulses of the received stream, 2π fp = ωp).

A significant ωfr / ωp mismatch (much larger than the capture range) is often the case, in particular in large volume, cost-effective monolithic implementation, where the VCO free-running angular frequency ωfr is no more accurate than about +/- 5% ( ICs manufacturing tolerances are not tighter than ± 25 %, but recourse to end-of-production trimming can correct them and reduce the inaccuracy range to something like within ± 5 % ).

The accuracy of fp is not the problem in modern networks, where it is better than +/- 50 ppm. It is the poor accuracy of the VCO free-running frequency ffr that makes the aid to the acquisition necessary. ωp = 2 π fp; ωfr = 2 π ffr
There are many more slave nodes than master nodes in a network, and the master nodes are more critical than the slaves. A larger cost (-> including a tighter accuracy) can be afforded for the masters, making ωp -that originates in a master node- (much) more accurate than ωfr -that originates in a slave receiver-.

Without aids the the capture range of the CDR is approximately coincident with +/-( jitter-in / jitter-out bandwidth) around the free-running frequency of the VCO.

If the free-running frequency is so shifted (away from the incoming pulse frequency) that the capture range does not include the frequency of the data to lock into, the phase comparator alone cannot make the acquisition possible.

The data transitions pass in front of the local clock faster than it can shift its frequency to catch one of them, with no chance to achieve phase lock.
In fact, these CDRs react in a time of about 1/(2 times the the capture range), and a new input transition shifts inside the range of the phase comparator (while the previous one drifts away), before a significant part of that time has elapsed.
The PLL goes through alternate periods of accelerating and decelerating, with slips in between, but never achieves phase lock.
Sometimes, when ωp is close to ωfr ± ωn2, a series of slips may eventually end in a good phase lock. The acquisition may be achieved but with slips and unpredictably long times.
Aided acquisition is then mandatory.

In such cases the acquisition must be aided by additional circuits that widen the capture range.

Inside a complex equipment another clock with good enough accuracy may be available. A frequency close to fp can be easily synthesized, and a frequency detector of clock differences can be used. Its output will be summed to the CDR PD output.
There have been also cases where frequency sweeping was used to have the capture range overlap fp.
Note that the VCO must be driven by a unique signal, even if the drive signal is obtained by combination of two separate ones. (A VCO with two inputs is a "bad idea" within the scope of stable control systems, see also [4] at page 261).

Tight jitter bandwidth and wide acquisition range can be achieved together if the CDR includes a Frequency Detector (FD) in addition to its Phase Detector (PD), as it is often the case[5].

Sometimes a separate FD for CDRs is used in parallel to the PD, but this is a rare occurrence.

The two blocks are normally physically and functionally combined, and the overall block/function is named phase-frequency detector PFD, which also offers the benefit of automatic transition from the operation of the one to the other as soon as lock is achieved.

A PFD may incorporate one to two linear PDs, but more often incorporates bang-bang PD(s) [6].

The bang-bang structure of the PFD in practical applications is a consequence of the application requirements. It will be shown that the (bang-bang) PFD is used in CDRs of the 2-2 type, that are made with bang-bang phase detectors.

Architectures of the 2-1 type normally find application in association with accurate VCOs, and architectures of the 1-1 type are used for phase aligners that have a perfectly accurate local clock by definition.

The frequency detection in practical applications is part of a monolithic implementation of the CDR, working at the highest speed that the chip technology allows. Then the implementation will be based on discrete time instants and binary signal levels, as mentioned already for PDs[1].

To reinforce the general validity of the above point, another aspect of the IC industry must be appreciated. When a new, faster chip technology appears, it will be used to create new CDRs at higher speed, as the mentioned paper[1] emphasizes. But this new technology will NOT be used for a redesign of the CDRs made in an earlier technology pushing that technology to its speed limit. The semiconductor industry is always short of good designers, and at the same time it is difficult to replicate exactly the performances of an IC in a different, though older, technology. Additionally, customers are reluctant to undergo again the cost of chip qualification. Scarcity of design resources, risk of not making a good replica and customer reluctance for a re-qualification, all cooperate to the result that a successful mixed-signal chip is practically never redesigned. This also implies that architectural alternatives of an existing solution (that become possible with the appearance of a later and faster technology) are practically never implemented!


In a CDR the Frequency Detector must accomplish a very basic, simple task: bring the VCO frequency close enough to the pulse frequency of the incoming signal, so that the Phase Detector can take effect and drive the phase lock.

Simple tasks mean simple requirements: the Frequency Detector need not be linear, need not offer the highest gain possible, it shall just ensure a reasonably fast frequency acquisition for realistic frequency differences and must become unnoticeable as soon as the Phase Detector is able to take over. The important performance of the CDR are influenced by the PD, not by the FD: the FD is just required not to limit the PD performances.


The PFD used in CDRs are of the bang-bang type. The FD function is active outside of the frequency range where the PD can capture the incoming signal, and the FD effect disappears completely as soon as the PD function can take over.

This is why the Frequency Detector is normally neglected in modeling and often also in simulation of the CDRs.

Methods of frequency detection in CDR[edit]

Many different types of PFD for CDR can be conceived, with different levels of complexity and performance.

As explained in the previous paragraph, the PFD for CDR is actually implemented in the simplest possible form.


It has been shown earlier that to detect a phase difference in the CDR, the transitions of the data signal are compared with the transitions of one clock.

To detect a frequency difference fp - fVCO, the transitions of the data signal shall be compared with the transitions of two clocks of equal frequency (fVCO) that just have a constant phase distance. (= difference):

fp = ( φp(t1) - φp(t0) ) / (t1 - t0)
fVCO = ( φVCO(t1) - φVCO(t0) ) / (t1 - t0)
  1. the only time-base available in a CDR to generate t1 and t0 is the VCO itself. In fact, t1 and t0 shall come from VCO dedicated waveforms (= clocks).
  2. t1 and t0 shall have a fixed phase distance inside the VCO cycle.
fp - fVCO = ( φp(t1) - φp(t0) ) / (t1 - t0 ) - ( φVCO(t1) - φVCO(t0) ) / (t1 - t0 )
fp - fVCO = [ ( φp(t1) - φp(t0) ) - ( φVCO(t1) - φVCO(t0) ) ] / (t1 - t0 )
fp - fVCO = [ ( φp(t1) - φVCO(t1) ) - ( φp(t0) - φVCO(t0) ) ] / (t1 - t0 )


Two comparators[edit]

In the right hand side of the last equation, the two differences of the nominator have been highlighted with bold characters and underlined.

They represent the outputs of two phase comparators, the first comparing the data transitions with transitions ( of a VCO clock ) in t1 , and the second comparing the data transitions with transitions ( of a second -shifted- VCO clock ) in t0 .

Each individual phase difference will vary with time, and indicate a constant frequency difference if it exhibits a cyclic behavior, but neither alone can tell the sign of the frequency difference!

Combining the results of the two comparisons together it is possible to identify also the sign of the frequency difference.

( Provided the two clocks do not differ in phase exactly by 00 nor by 1800: the frequency difference signal would be completely attenuated in those two extreme cases!
The two phase comparators -different just because their two versions of the VCO clock are separated by 0° or by 180°- would always produce either coincident results or always complementary results, i.e. the very same information!
Note that phase comparators used in CDRs have a characteristic that is periodic with an odd symmetry and that is growing and monotonic inside each period.

The best discrimination (= the most robust signal) is obtained when the distance between the two identical comparators is chosen to be exactly 900 (or 2700).


Two clocks with 50% duty-cycle and separated by 90°[edit]

Two clocks with 50% duty-cycle and orthogonal with each other (that is 900 or π/2 out of phase) make the two phase comparators divide all the 3600 of their period into 4 quadrants.

The two phase comparators together indicate the quadrant where the data signal transition is located, and this info can be updated at every new data transition.

This type of frequency detectors are called "rotational" frequency detectors[7][8].
In the same paper Donald Richman first introduced the term "quadricorrelator" applying PFD to NTSC color carrier detection in color television and describing an analog version of the circuit that uses both an In-phase and a Quadrature clock to obtain a beat note at double frequency and a d.c. component proportional to the frequency difference. (Quadrants defined with Phase and Quadrature clocks, hence the name quadricorrelator). Although the quadricorrelator operation may not be very good with the random transitions of a NRZ data stream without some modifications ([4] page 269), the I and Q technique is good also for CDR PFDs.
  • I (lag in the figure), is the reference and defines with its positive transition the 0o instants. I stands for In-phase; (When PD and FD are combined and part of a CDR, then I is the clock used for data regeneration).
  • Q (lead by 90° in the figure) identifies the -90o or 270oinstants. Q stands for "Quadrature".
Two synchronous clocks, 90 degrees distant from each other, divide each period T in two intervals, 1/4 T and 3/4 T.
If the two clocks have 50% duty cycle, using their negative transitions, all 4 quadrants can be identified.
I is the reference, In-phase clock, Q leads I by 90 degrees.
Before lock, the data transitions shift with respect to the two clocks.
When a data transition is first detected inside the interval "I leads Q" and then detected inside the interval "Q leads I", the data transitions are shifting to the left.
The data transitions are therefore based on a frequency lower than the frequency of the two clocks.
In such condition, the VCO of a PLL shall be driven towards a lower frequency, that is with a lower level of the VCO drive signal.
When a data transition is first detected inside the interval "Q leads I" and then inside the interval "I leads Q", the data transitions are shifting to the right.
The data transitions are then based on a frequency higher than the frequency of the two clocks.
In such condition, the VCO of a PLL shall be driven towards a higher frequency, that is with a higher level of the VCO drive signal.

If the two I and Q clocks have both 50% duty cycle, using also their negative transitions, all 4 quadrants can be identified.

The frequency sign can be obtained each time the data transitions, after a detection in a given quadrant, cause a detection in a quadrant to the left (fp lags fVCO), or to the right. (fp leads fVCO)

Bang-bang = just the sign of the frequency difference[edit]

The PFD is mostly used for monolithic CDRs made with the 2 - 2 architecture, where the Phase Detector is of the bang-bang type.

Therefore the PFD will be of the bang-bang type as well.

  1. the two PDs of the PFD are of the bang-bang type to start with. Their outputs only give one bit indication. The nominator in the PFD formula is reduced to a sigle bit as well. (Or to a "ternary" type of output, if the overall CDR needs minimum jitter generation).
  2. the time difference in the denominator of the PFD formula is a fixed fraction of the local clock (=VCO) cycle. It has always a positive sign, even if it may vary (inversely) with the VCO frequency. Therefore it is disregarded in a bang-bang PFD (replaced by a constant +1).

In other words, the PFD will just output an indication as simple ( binary or ternary ) as the phase detector that operates on its I clock.

How a bang-bang PFD is made[edit]

It is made up of two PDs and one final block that processes the outputs of the two PDs.

One PD operates on the input data stream and on the VCO clock that shall be locked to the data. This clock is called the I (= In phase) clock.

The other PD operates on the input data stream and on a VCO clock that is 90°, i.e. π/2, out of phase with the previous one. This clock is called the Q (= Quadrature) clock. It could be be +90° or -90° out of phase with I : let's choose here +90°, which means that the Q waveform lags the I waveform.

In a typical example, the two outputs from the two PDs are put together in a following block that is essentially the same as the output stage of the "hold" bang-bang PD.

The scheme of principle of a bang-bang PFD for CDRs.

This structure works with signals as follows:

  • the clocks of the first PD are:
  1. the clock that regenerates the data and
  2. its 180° shifted version
  • the clocks of the second PD are both shifted versions of CK0 that regenerates the data, respectively:
  1. by 90° and
  2. by 270°,

which partitions the VCO period into the four quadrants already mentioned.

The two clocks of each PD are 180° out of phase with each other.

The outputs of the two PDs are combined in a final stage identical to the final stage of the "hold" PD: this PFD becomes a "hold" (= binary) PFD.

The output of the PFD may be present a polarity inversion if:

  1. the shift of the Q clock of the second PD is -90° instead of +90° with respect to the clock I (the other clocks do not matter, as +180° is indistinguishable from -180°);
  2. the final stage either uses an inversion after the top flip-flop or an inversion after the bottom flip-flop.

An example of the waveforms in case of a constant frequency difference is shown in the following figure (note the inversion of the PFD output):

Simulation (with 3000 time points) of the waveforms inside a Phase and Frequency Detector of the bang-bang type.
The detector is driven by one clock (input +) at 1 GHz (i.e. DT = 100%) and by another clock (input -) at 1GHz-398 ppm.
After 1850 simulation samples, the input clock becomes noisy with the addition of a sinusoidal phase jitter of 0.3 rad of amplitude and of 10e+10 rad/sec of angular frequency.
Note the typical pattern of the slips of the outputs of the two Phase Detectors driven by I(lead) and Q(lag), that are orthogonal square waves separated by 1/4 of the beat period.
The wave of the Q (lag) detector seems to lead the other: this is because the frequency difference is negative.
This PFD is wired so that its output is low if the negative input receives a lower frequency than the positive input, and viceversa.
In many cases the output polarity is the opposite.

This system is a discrete time system with samples at frequency fVCO, and a data transition should be sampled at least once every time it drifts through one of the four quadrants. Each drift trough a quadrant should last at least 1/ (4fVCO).

A data transition has been sampled inside one quadrant. The following data transition (DT = 100%), while the data stream drifts across the quadrants defined by Q and I, should preferably be sampled (at least once) inside each quadrant. The sampling takes place if the period of 1/fVCO stays inside the range 1/fp +/- 25%.

DT is normally lower than 100%. The maximum Δf that this type of PFD can detect is ±25%, even if the technique of "hold"ing the detection when no transition is present could extend the theoretical range to ±50%.

If the frequency difference to detect is in the range of ±15% or larger, then it is preferable that the two PDs artificially "hold" the previous detection of the phase until a new significant detection can be made, and that the FD does the same (Binary PFD[1] ).

If instead the frequency difference to detect does not exceed ±10%, then the two PDs might still be of the "hold" type, but the last PFD stage would be improved to a "free running" type (Ternary PFD [1]).

The feature can be obtained in principle by a retrofit that:
  • extracts also the T signal from the PD operating on the I clock
  • drives the charge pump following the PFD output with the two signals: UP = T + E  ; DOWN = T*E.


A bang-bang Phase Detector that "holds", in a different representation[edit]

This kind of PD has already been introduced in the previous page about PDs.

It is presented again here with identical behavior, but using a different set of circuit symbols that better represent the circuit elements of a high-frequency integrated circuit.

High frequency circuits are fully differential for noise immunity, making a signal and its complement always available together. Exchanging one wire with the other of a differential pair corresponds to the inversion of the signal: no inverter stage is needed. Multiplexers are easy to implement. Two flip-flops and a multiplexer make up a double edge triggered flip-flop DETFF.

In this case, the two DETFFs allow the use of clocks at half the frequency because both edges of the clocks are used (clocks must have 50% duty cycle).

The clocks that drive the two flip-flops, are indicated as the I (lead) and Q (lag, i.e. 90° late) clock phases coming out of an oscillator that runs at half the data pulse frequency. They are equivalent to two clocks of double frequency and separated by 180°.

This anticipates the incorporation of two of these PDs in a PFD that uses their outputs to detect the sign of the frequency difference, in a CDR that uses a muli-phase VCO at half the frequency.

A bang-bang PD with output held fixed if the incoming data miss one or more transitions, rendering the PD gain independent from the transition density.

The output of the first DTEFF carries the regenerated data, the output of the second DETFF carries the cross-over samples taken at the instant when a data transition is expected.

It may be noted that this PD is made up of three DETFFs, but the third is slightly modified with an inversion at the output of its upper flip-flop.

This inversion in the upper branch of the last stage sends to the output:

  • the last cross-over sample when the data have a positive transition (and as long as they stay high);
  • the opposite of the last cross-over sample when the data have a negative transition (and as long as they stay low).

Inverting on negative transitions and not inverting on positive ones makes the PD output go high if the clock lags the data, and viceversa.


A bang-bang PFD with reduced VCO frequency for easier implementation inside an IC[4][edit]

The following figure redraws the PFD presented earlier changing two aspects:

  • the elementary blocks of high frequency monolithic circuits are used (DETFF, differential connections and the multiplexer),
  • the input clocks come from a VCO at half the frequency.

A very similar one, just with I that lags Q, is described in [9].

A bang-bang PFD that can be driven by a VCO at f/2
The inversion placed on the upper flip-flop of the final stage causes the PFD to a high output if the VCO frequency is lower than the data frequency, and viceversa.
The inversion on the lower flip-flop would cause a low PFD output when fVCO < fp and a high output when fVCO > fp.

The Q clock lags the I by 90°. When acquisition is achieved, CK0( i.e. I) is where it should be. The PD2 will output a constant 1, because Q is late by exactly 90° and should accelerate.

But in this condition the output of PD1 is replicated at the output of the PFD and drives the PLL alone. PD2 remains constantly at 1, phase-locked into its 90° lag state by the PLL operation.

Otherwise said, when the PFD is part of a CDR that reaches the phase lock, its output replicates the output (or the inverted output) of the PD that acts as clock of the PFD final stage.

This means inverting the output of the top flip-flop in the final stage if the second PD uses a clock 90° late (like in the waveforms below and in the schematic of the figure above), and inverting the output of the bottom flip-flop in the final stage if the second PD uses a clock that is 90° early.

The figures that follow represent the waveforms at the external connections as well as at the internal nodes of one PFD like in the figure above.

The first figure describes the case of an input signal with the highest possible DT (i.e. 100% and a data pattern 101010..).

The second figure describes the case of an input signal with a random data pattern.

In both cases the clocks (nominally at half frequency) and the input data of the PFD correspond to frequency ratios different from the nominal value of 50%.

Waveforms inside a bang-bang Phase and Frequency Detector for CDR use.
The PFD receives a fixed pattern 101010 of data NRZ input and the 4 phases of a clock at f/2
with a constant frequency difference between the data frequency and (twice) the clock frequency.

In the case of maximum transition density (in spite of a large frequency difference) the waveforms are as regular as it could be expected. The two phase detectors toggle at the beat frequency, and overlap each other transitions.

The PFD output (almost) immediately reaches a stable indication of the sign of the frequency difference. In a closed loop this means the fastest possible acquisition transient.

Waveforms inside a bang-bang Phase and Frequency Detector for CDR use.
The PFD receives a random data NRZ input and the 4 phases of a clock at f/2
with a constant frequency difference between the data frequency and (twice) the clock frequency.

With a random pattern of the received pulses, the waveforms are much less regular.

As a result, the PFD output is far from stable, but at least its average deviates from 50% enough to give a clear indication of the frequency difference.

Every time the generation and recording of these waveforms are repeated, the figure for 101010 data is practically the same.

The figure for random input data instead changes significantly with the change of the sample of the input pattern, but the average value of the PFD output, although variable as well, remains on the correct side of 50%.

Acquisition of Frequency and Phase Lock[edit]

The following example refers to a CDR with a 2 -2 architecture, incorporating a PFD like the one described in the previous paragraph.


Simulation of the acquisition phase of a PLL 2nd order type 2 with a bang-bang Phase and Frequency Detector.

The figure is obtained by a simulation with 3000 time steps.

The waveforms of the two Phase Detectors are shown at the top, translated higher not to overlap the analog waveforms.

Neither the line pulse sequence nor its frequency are used in the simulation of the waveforms of the voltages and angular values depicted.
Therefore the Q clock operation is simulated by the trick of replicating at the PD2 input the input signal phase with a 90° shift (= delay, Q lags I).

Initially (100 time steps) no signal is present, LOS is asserted and the VCO runs free.

Then the signal appears (LOS=0), and the frequency locks begins.

The PD1 and PD2 gains correspond to the maximum transition density, to simplify the simulation and to shorten the acquisition for easier fitting inside the figure.

After about half a μsec the square waves coming from the two PDs widen clearly their periods and the filter output follows a linear ramp towards the driving voltage that brings the VCO to the lock frequency.

After a little more than 3 μsec and some phase undershoot the acquisition is complete.

The bang-bang tracking begins, and the output phase tracks the input (that has a slight downward slope because its frequency is slightly lower than its nominal frequency).

The error function becomes stable at about -50 rad, that correspond to the slips before lock.

Sometimes later, a little before 6 μsec have elapsed, a substantial input sinusoidal jitter appears. The filter output shows that the limits of tracking ability of the loop are slightly exceeded during every jitter cycle. But not much, as the error function does not show a strong evidence of it.


External References[edit]

  1. a b c d e Richard C. Walker (2003). "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7. http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf. 
  2. http://www.unhas.ac.id/rhiza/arsip/research-stuffs/Phase-Locked/218-PhaseDetector-2.pdf
  3. Clock Recovery Primer, Part 2 by Guy Foster, par.10: Survey of Clock Recovery Used in Selected Standards
  4. a b c Aaron BUCHWALD Hong Kong University of Science & Technology, Kenneth W. MARTIN University of Toronto Toronto, Ontario, Canada. "Integrated Fiber-Optic Receivers". http://www.mobius-semiconductor.com/whitepapers/IntegratedFiberOpticReceivers_crop.pdf. 
  5. Behzad Razavi, Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits-A Tutorial, 4.6 Aided Acquisition, downloadable at: http://itee.uq.edu.au/~coms3100/coms3100/Lecture%20Notes/Razavi1996_PLL_IEEExplore.PDF
  6. S. Tontisirin and R. Tielert, 2.5 Gbps clock data recovery using 1/4th-rate quadricorrelator frequency detector and skew-calibrated multi-phase clock generator, Adv. Radio Sci., 4, 287–291, 2006 http://www.adv-radio-sci.net/4/287/2006/ars-4-287-2006.pdf © Author(s) 2006. This work is licensed under a Creative Commons License. Advances in Radio Science
  7. Donald Richman. Color-carrier reference phase synchronization accuracy in NTSC color television. Proc. IRE, 42:106–133, January 1954.
  8. P.E.Allen, June 26 2003, Lecture 200 - Clock and Data Recovery Circuits from ECE 6440, page 200-15..17, http://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L200-CDR-I(2UP).pdf
  9. Jafar Savoj and Behzad Razavi, A 10Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection, ISCC 2001