Clock and Data Recovery/Structures and types of CDRs
At the receiving end of a data transmission link, the received signal is amplified, filtered and equalized. Then a “slicer” circuit reshapes it and retains just the level transitions and the levels that represent the nominal values of the received signal in that interval between two consecutive transitions. The CDR processes the “sliced” signal
 to extract the clock signal embedded in its transitions (clock recovery) and
 to sample and retime the pulses of the “sliced” signal (data recovery).
Clock recover circuits include:
 the phase locked loop architecture (PLL)  the most common method of clock recovery
 the synchronous oscillator  much less common, but which may claim, in certain cases, some advantages over PLL^{[1]}
 the gated oscillator, that resembles the synchronous oscillator, and that is useful when very fast acquisition is needed and other performances can be traded off in return for it^{[2]}
Many good books are available, with theory and practical examples, like^{[3]}.
It is useful however, in order to get the best out of them, to have the ability to recognize in each case the fundamental architecture, that is the "Control Systems" block diagram that corresponds to the actual circuit.
Contents
Importance of good reference models[edit]
The function of a CDR is a relatively simple one. The architectures possible for it are, accordingly, just a few and simple ones (actually just three!). It is nonetheless important to have a good knowledge of those architectures and a good understanding of their mathematical descriptions because these models are the best tools for the engineer that must deal with CDRs.
 Starting from the definition and specification of (a communication system and of its) CDR(s),
 and all the way through all the different engineering tasks that logically follow
 (like design, verification, validation, manufacturing tests, failure analysis, system operation and maintenance),
 those models can be an invaluable reference for the engineer.
 He will need them to imagine, specify, design, check, measure and interpret the behavior of a CDR.
The actual implementation of the CDR may differ from the neat, simple analog structure that the mathematical model depicts. Complex digital blocks, DLLs, DSPs may render the analogy difficult to detect, but the fundamental signals and operation of the CDR can not differ. Yielding to the temptation of forgetting the models is a very risky and error prone short cut.
The essential signals and blocks of the architecture must be clearly identified in the actual system. The use of the reference model will then be the best way to make sure that all aspects of the CDR operation are identified and taken into consideration.
The CDR is always designed with the architecture of a PLL (with the obvious addition of the regeneration block, where the received pulses are resampled with the local clock). Let’s study the PLL, that is the essential part. It should be kept in mind that such PLL will be specialized for application inside a CDR.
The PLLs inside CDRs are in all cases of the unity feedback kind. The input of the circuit is the phase of a reference signal (a clock or a serial data signal) and the output is the phase of a signal (a serial data stream or a simple clock). The output is locked as much as the circuit can to the input signal. The input signal is contrasted with the output signal in a phase comparator, whose output is the error signal. The error signal is processed and then used to control another circuit block that produces the output clock signal.
Essential parts of a CDR[edit]
It is important to identify the essential parts (listed below) of the CDR system but also to identify where the received signal and the local clock fit in the architecture. Either one (the received signal or the local clock) may act as input, while the other would simply act as an internal input signal inside the block called “Controlled element” (the block that generates the output signal of the PLL).
The received signal acts as reference input for the PLL when the PLL function is to generate a clock slaved to the received signal itself.
The local clock acts instead as reference signal for the PLL when the PLL function is simply to “phase align” the received signal to it, in the cases where the received signal timing is derived from the local clock itself (following a short loop inside a unique clock domain where the local clock is master).
The list of the parts that shall be clearly identified in the CDR are:
 the phase information (carried by the level transitions) of the received signal
 the phase information (carried by the level transitions) of the local clock
 the phase comparator that measures the relative phase of the local clock with respect to the phase of (a signal related to) the received signal
 an integration block (1/s in the language of Control Systems) or an accumulator if the implementation is of the discrete time type. It makes the control loop able to squeeze down to zero the steady state frequency error (and to a negligible value the corresponding phase error)
 the regeneration of (a signal related to) the received signal by the local clock.
Order and type of a CDR [edit]
Order[edit]
The order of a control loop (causal, linear and time invariant in our models of CDRs) is the order of the differential equation that describes it.
In the language of control systems, the order is the number of poles of the (open or closed loop) system transfer function.
 1^{st} order systems are unconditionally stable, are characterised by one parameter only and are a good model to represent CDR PLLs that have been deliberately designed with a simple behaviour…….
 2^{nd} order systems are unconditionally stable, are characterised by two parameters and can be used to model practically all CDR PLLs for which the 1st order model is too simple.
 3^{rd} and higher order systems are not of practical use in the study of CDRs. They may be unstable in some conditions and, moreover, they are more complex to use but do not offer a better behavior for CDR use than the 2^{nd} order systems. ( Some complexity beyond the simple 2^{nd} order system can be useful to model more accurately some parasitic effects of a CDR circuit, but not to design nor to model performances within the range of functionality of the CDR).
Type[edit]
The type of a control loop is the number of poles of the open loop transfer function in the origin (that is, how many times the factor 1/s appears in the open loop transfer function).
The type of a loop tells how well the loop itself is able to track a deviation of its input signal from the nominal value.
(A CDR can operate with a small phase (= sampling time) error without deterioration of performances, provided the error is small enough: a few degrees of jitter around the optimum sampling time do not deteriorate significantly the bit error rate!)
 Type 0 systems are able to track a step function ( a phase deviation of the input from the nominal phase expected by the circuit itself) with a small, but finite error. A type 0 PLL can not track at all a linear ramp of phase variation in the received signal (that is a step change of the frequency of the received signal with respect to the frequency of the free running local oscillator!). Therefore they are not of large use for CDRs.
 Type 1 systems are able to track signals that exhibit a step change of phase, without steadystate error. They are not able to track unit ramp inputs without a finite error, though.
CDRs are very often type 1 systems, because they can be designed to phase lock: with zero phase error when there is no frequency (just phase) difference
 with a very small phase error when the master clock embedded in a received signal stream and the free running frequency of the local oscillator are close together.
 Type 2 systems are able to track signals with a frequency different from the their free running frequency, without steadystate error.
(As type 2 implies by definition at least 2^{nd} order or higher, just the type 2 of 2^{nd} order is to consider).
In practice the 2^{nd} order type 2 architecture is used because a constant frequency mismatch can be tracked with zero error independently of the loop gain.
This is unfortunately accompanied by a softer rejection of the input jitter (= input signal noise) at high frequencies.
When the loop gain is variable in a very wide range (because of a bangbang phase detector or because of a highly variable transition density), this architecture is often preferred.
Loop type and steady state error[edit]
General case[edit]
when the input (besides sinusoids of any frequency and magnitude), includes
a constant, or a step function, or a ramp function, etc.,
The steady state error, when it exists and is finite and nonzero, can be computed from the open loop transfer function:
using the following table, that resumes the most important formulas for the systems representing CDR architectures:
System type and input signal  Unit step  Unit ramp  Unit parabola 

Type 0  
Type 1  
Type 2 
1st order loop[edit]
The open loop transfer function (this loop and its equations are described further down in Examples of CDR structures: 1^{st} order, type 1, Oscillator controlled in frequency ("first order slave CDR")) :
 For a type 1 system let's define the auxiliary quantity K as :
K =
In the case of our 1^{st} order system which is a type 1 system:
The steady state error in case of a unit ramp of the input phase is:
 The unit phase ramp function is:
 0 [rad] when t < 0
 (1 [rad/sec] ) * t [sec] = t [rad] when t >= 0
The steady state error is generated in practice by the frequency offset between the frequency of the incoming line pulses ( [2π rad/sec]) and the frequency of the VCO when the latter is driven by the indifferent (e.g. 0 volt) level of the filter output, ( [2π rad/sec]). ( is also called the VCO "freerunning" frequency ) The steady state error due to the frequency mismatch is:
This steady state error appears as an offset of the sampling instant away from its optimum point at the center of the received eye.
2^{nd} order loop[edit]
For a type 1 system, the open loop transfer function (this loop and its equations are described further down in The CDR based on a second order PLL: Fundamental equations) :
 The auxiliary quantity K is defined as as :
In the case of our 2^{nd} order system which is a type 1 system:
The steady state error in case of a unit ramp of the input phase is :
 The unit phase ramp function is:
 0 [rad] when t < 0
 (1 [rad/sec] ) * t [sec] = t [rad] when t >= 0
The steady state error is generated in practice by the frequency offset between the frequency of the incoming line pulses ( [2π rad/sec]) and the frequency of the VCO when the latter is driven by the indifferent (e.g. 0 volt) level of the filter output, ( [2π rad/sec]). ( is also called the VCO "freerunning" frequency )
The steady state error due to the frequency mismatch is:
This steady state error appears as an offset of the sampling instant away from its optimum point at the center of the received eye.
For a type 2 system the steady state error generated by a frequency offset between the frequency of the incoming line pulses ( [2π rad/sec]) and the freerunning frequency of the VCO, ( [2π rad/sec]), is exactly 0, as can easily be derived in analogy with the example of the type 1 system.
Non essential differences[edit]

 Flat gain block. In a first order loop a flat gain circuit stage often precedes the VCO. The designer can choose the overall loop gain (an important CDR parameter) without the constraint of the VCO gain value, that is forced by technological choices. Sometimes this block is clearly identified, sometimes it is represented as one with the VCO. This is decided according to what has to be emphasized, but does not change the loop order at all.
 High frequency rejection. There is always some sort of filtering at the output of a phase comparator, to reject high signal frequencies (around f_{p} and its harmonics) as well as noise. Only the phase signal at (much) lower frequencies is of interest for the CDR operation. This filtering can be neglected within the scope of our study, as it does not turn a first order loop into a second order loop, nor a second into a third.
 Second order order loop with high ζ value. When ζ is greater than 1, there are two real poles in the loop and the one that creates the jitter cutoff frequency is more important. When ζ is significantly greater than 1, the pole that generates the jitter cutoff is dominant for the loop behavior. A loop with ζ significantly greater than 1 is very similar to a first order loop whose pole coincides with its dominant pole. Second order loops with ζ greater than 6 are of no interest for the CDR theory and applications.
Why only these three?[edit]
There are plenty of possible architectures, and for each pair order/type there are several different architectures.
But just three are valid for CDR PLLs. Why no other?
It has been anticipated that in a network phase aligners and slaves are needed:
CDR function  Recovered data  The slave clock  Timing  CDR requirements 

END POINT  passed into another clock domain  used throughout, then discarded  SLAVE  Jitter tolerance 
REGENERATOR  sent forward with the recovered clock  used throughout and sent forward to extend the clock domain  SLAVE  1. Jitter tolerance 2. Little noise generation 3. Filtering out incoming noise and unwanted jitter 
PHASE ALIGNER  sent forward with a cleaner local clock  used initially, then discarded  emancipated to a cleaner local clock  Jitter tolerance 
Here are the reasons in detail for the 3 architectures (note that there are 3 network functions and 3 architectures, but that they do not correspond exactly one to one):
 All CDR PLLs are unity feedback loops. The phase of the output signal (= of the local clock that locks into the incoming signal level transitions) must be directly compared with the phase (the level transitions) of the input signal.
 Note that this definition holds good for all CDR PLLs, including the phase aligners. In this last case though attention must be paid to identify correctly the output signal of the PLL that is not the independent clock that the input signal must be aligned to, but the clock generated by the PLL and used to write into the elastic buffer.
 Contrary to CDR PLLs where input and output frequencies are the same, frequency synthesizer PLLs often have circuitry that makes the output frequency an m/n multiple of the input, and part of it is located in the loop feedback path.
 The order of the loop can only be one or two. Order 0 cannot lock, while order 3 and higher are prone to unstability or do not add any advantage .
 The type must be at least 1 (which limits the possible choices to the three cases), to achieve phase lock. Therefore a loop of 1^{st} order can only be used if of type 1, while a loop of 2^{nd} order can be either type 1 or type 2 (the type cannot be higher than the order, by definition).
 For the 2 loops of order 2, the filter block (that must be of order 1) must be a low pass ( ω_{p} < ω_{z} ), because the jitter and noise of higher frequencies must be more, and not less, rejected. Considering all types of order 1 filters:
1^{st} order filter block inside a 2^{nd} order PLLs for CDR applications  Notes  

Frequency of the pole  Frequency of the zero  Loop natural frequency ω_{n1} = 1/G ; condition to avoid underdamping: 
The pole must be at a higher frequency than the zero 
0  ω_{z}  ω_{n1} ≥ ω_{z}  The 2^{nd} order PLL is of type 2 because of the additional pole at zero frequency added by the filter block. 
ω_{p}  ω_{z}  ω_{n1} ≥ ω_{z}  If ω_{z} ≫ ω_{p}, the case is similar to the one above, with poorer performances. 
ω_{p}  ω_{z}  If ω_{z} ≈ ω_{p}, it is like having a flat gain block instead of a filter. The PLL behaves like an order 1 type 1 PLL.  
ω_{p}  ω_{z}  ω_{n1} ≤ ω_{p}  If ω_{z} ≫ ω_{p}, the case is similar to the one below, with poorer performances. 
ω_{p}  ∞  ω_{n1} ≤ ω_{p}  The 2^{nd} order PLL is of type 1 because no additional pole at zero frequency is added by the filter block. 
In conclusion:
 for a phase aligner, that only needs a good jitter tolerance, the 1 – 1 is chosen, because of its fast acquisition, good tolerance, and robustness against both nonlinearity and drift of characteristic in the circuit components.
 for slave CDRs, the (slave) PLL architectures 21 and 22 are chosen.
The following pages of this book shall show that the best matching of applications and architectures is:
Applications  Architecture  linear or bangbang ? 

Burstmode and phase aligner  1^{st} order and 1^{st} type  bangbang det. + accum./DLL or bangbang VCO 
Regenerator  2^{nd} order and 1^{st} type  linear 
Monolithic highspeed and/or zero steadystate error  2^{nd} order and 2^{nd} type  bangbang det. + charge pump 
External References[edit]
 ↑ "The Synchronous Oscillator" James A. Vincent, 1993
 ↑ Minhui Yan^{a}, Xiaobin Hong^{a}, WeiPing Huang^{a}, Jin Hong^{b}  a: Department of Electrical and Computer Engineering, McMaster University,Hamilton, ON L8S4K1, Canada; b: Oplink Communications Inc., 46335 Landing Parkway, Fremont, CA 94538, USA Design of Highspeed Burst Mode Clock and Data Recovery IC for Passive Optical Network.  Photonic Applications in Devices and Communication Systems, edited by Peter Mascher, Andrew P. Knights,John C. Cartledge, David V. Plant, Proc. of SPIE Vol. 5970, 59702W, (2005) · 0277786X/05/$15 · doi: 10.1117/12.628728
 ↑ Behzad RAZAVI, Monolithic PhaseLocked Loops and Clock Recocvery Circuits . Theory and Design. IEEE PRESS 1996  ISBN 0780311493