Clock and Data Recovery/Structures and types of CDRs/Applications of the 2nd order type 2 architecture

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Reference is made to the simulator program available at: (a new version is in preparation --BORGATO Pierandrea 14:12, 1 September 2013 (UTC)

This architecture uses the option of a zero (the gain increases at lower frequencies) in the filter stage between phase comparator and VCO.

There is pre-emphasis (-20 dB / dec) of the frequencies lower than ωz in the stage between comparator and VCO, that makes the loop a second order type 2 loop. The response to an input variation always ends with catching up completely (zero steady-state error), but also (as long as the loop gain is not "infinite" or the "latency" is relevant [1] ) overshoots significantly.

The maximum output of the comparator corresponds in practical applications to much less than the maximum frequency deviation of the VCO, deviation that can be exploited gradually thanks to the integration of low frequencies made the filter stage between comparator and VCO.

It is like using either the accelerator or the brake, increasing pressure indefinitely on the pedal until the response of the system becomes sufficient.

It is easy to understand how this architecture reacts immediately but only to a limited extent, and then increases the correction slowly but progressively if the immediate response has not proven sufficient.

A low gain at high frequencies may be chosen to attenuate more the high frequency input jitter (in many cases also to attenuate the bang-bang tracking jitter) while the integration of the input phase error (assisted by a PFD) provides for acquisition in a much wider range of input frequencies.

Where used and how made[edit]

This architecture finds its practical applications where a bang-bang phase detector must be used and where the Es must be reduced to a minimum (possibly zero).

The strong reduction of the low-frequency noise from the VCO is a further bonus.

A bang-bang phase detector is inevitable in monolithic applications at very high line frequencies [1], and monolithic implies also an on-chip oscillator, that is relatively noisy and relatively inaccurate in ωfr.

As the 2-2 architecture is well suited for monolithic implementations, this explains its widespread use.

On the other hand, the high volume applications of today are correspondingly very cost sensitive, and require that a single silicon chip accommodate the whole CDR, and also much more.

In practice a bang-bang phase detector is always used, and the VCO is a linear monolithic one, either a ring oscillator or a low-Q LC.

Consequently all the monolithic:

  • line regenerators,
  • slave clocks in Telecom networks
  • CDRs of portable electronics

are made with this 2 - 2 architecture.

A long run-length can affect the tolerance margin in sampling the received signal, but this is normally mitigated by the use of a ternary phase detector.

This loop type is the most “powerful” of the three, because it incorporates a loop filter that offers a very high gain at low frequencies.
This is the characteristic feature of this architecture, that generates its strong and weak points.
The high gain at low frequencies allows the compression to very low value of any steady state error, unlike the other two loops ( 1 - 1 and 2 - 1 ). The filter gain is maximum at very low frequencies, and decreases up to ωz, then it flattens to the asymptotic value and stays constant in the bandwidth of interest (until parasitic poles, always present, make it drop). Gf is very low, in all cases below 1, so that it is often referred to as "the filter attenuation".
The flat gain of the loop filter at high frequencies allows a good tracking of medium frequency jitter, unlike the other second order loop ( 2 - 1 ).
The very low gain of the loop filter at mid and high frequencies keeps the tracking jitter (i.e. the jitter generated by the bang-bang frequency jumps) adequately low.
The high gain at low frequencies allows the frequency and phase acquisitions even when the VCO free-running frequency is shifted much more than ωz from the frequency of the signal to recover.

This 2 - 2 loop tracks very well, as long as the loop filter and the VCO operate within their range of normal operation.

Care must be paid to the very high (closed loop) gain at low jitter frequencies when either:

  • the lack of data transitions temporarily opens the feedback path (this is mitigated by the use of a ternary PD, but presents anyway the risk of a phase error that may increases out of control as long as the loop is open);
  • the (sinusoidal) input jitter has a significant amplitude. The filter gain at high frequencies is kept low to limit the jitter generation resulting from the bang-bang, but this limits the ability of the loop to track a fast and large swing of the input phase. The jitter tolerance depends on the corner frequency of the loop filter and on the length of runs without transitions.
Closed loop gain and corner frequency of the tolerance curve are concepts easily identified if the loop is linear.
When the loop incorporates a bang-bang detector, and the data transitions are random, it is necessary to restrict the study only to conditions of practical interest and to use simulations.

Introductory example[edit]

This simulation diagram helps understand the operation of the 2 – 2 architecture with bang-bang phase and frequency detector.

The two waveforms of the two phase detectors of the PFD are shifted higher in the diagram, for easier interpretation. The other waveforms are not shifted.
The outputs of the PFD and of the loop filter are scaled differently, with the filter output more amplified in the representation. (The filter output does not reach the clamping level(s), and the VCO drive signal is not different from it, i.e. would be exactly overlapped to it in the diagram. The high frequency parasitic pole of the charge pump is at 200 Mrad/sec, and its effect is barely visible in the shape of the filter bang bang spikes).
To the left the waveforms show that there is no incoming signal. LOS is asserted and the loop is open. The VCO (=the CDR) output simply drifts away with a slope proportional to the difference between the signal frequency and the VCO free-running frequency.
After 1.28 μs (= 150 simulation steps) the signal appears with a phase mismatch equal to -4.0 radian, which happens to reduce the cumulated phase drift that had reached 10.06 rad.
LOS is dis-asserted at that moment and the loop starts catching up.
Initially the output of the PFD is a constant positive level (meaning the VCO is slower than the incoming signal. The filter, that integrates the low frequencies of the comparator output, adds a further positive ramp.
The output phase undershoots the input phase before lock, with even a small overshoot when the filter makes the first negative bang and starts a negative ramp to finally reach a stable continuous bang-bang condition.
During the frequency acquisition three slips have createdted a gap of exactly 3 π between input and output. The gap remains constant from then on, apart from a small additional phase error.
As soon as the loop has caught up with the input, the typical pattern of bang-bang starts: the loop is in lock. The comparator bangs rapidly between is two output states and the filter output maintains a d.c. bias that compensate the ωp - ωfr distance.
After 8.53 μs (= 1000 simulation steps) the input signal phase starts a sinusoidal jittering with a large amplitude (3.20 rad) and a frequency of 0.9 rad/μs.
This jitter brings the loop close to its tolerance limit, which is shown by the detector and by the filter outputs that is alternatively forced out of bang bang, as well as by the error signal that shows deviations from its average of 3π-4 rad in correspondence with those periods of difficult tracking. The error signal deviations are not large in this case, and remain within +0.25 and -0.26 rad.

In this example the transition density is 100%, but the random nature of the input signal must also be taken into account.

Single zero filter[edit]

The zero is at angular frequency ωz =1/τz,
ωw = 1/τ is the frequency of gain = 1 = 0 dB . τz = Gf τ .

This loop type is the most “powerful” of the three, because it incorporates a loop filter that offers a very high gain at low frequencies, that is the key feature of the 2 - 2 architecture and that generates its strong and weak points.

The filter gain is maximum at very low frequencies, and decreases up to ωz, then it flattens to the value Gf and stays constant in the bandwidth of interest (until parasitic poles, always present, make it drop).
The high gain at low frequencies allows the frequency and phase acquisitions (a ternary PFD is used in these applications) even when the VCO free-running frequency ωfr is shifted much more than ωz away from the frequency ωp of the signal to recover.
The high gain at low frequencies allows the compression to very low value of any steady state error, unlike the other two loops ( 1 - 1 and 2 - 1 ).

The (almost) infinite gain at low frequencies gives this architecture some very useful properties, but it can also be the origin of unexpected troubles.

Unlike in the generic figure above, Gf is very low, in all cases below 1, so that it is often referred to as "the filter attenuation" and called β. As a consequence, ωz is higher than ωw, the zero-gain frequency.

In the 1 - 1 architecture the output of a bang-bang binary PD always makes the VCO jump from one end of its control range to the opposite end. This leaves a strong residual "tracking" jitter in the output phase of the PLL, because only the 1/s slope of the VCO characteristic does filter the sharp and large swings.
The 2 - 2 architecture in principle behaves the same for high frequency jitter as its loop filter does not filter out the high frequency components (higher than ωz) coming from the comparator output. The filter passes the high frequency components of the jitter to the VCO with a flat transfer function. But the value of the filter gain above ωz ( although flat up to where parasitic poles at even higher frequencies make themselves felt ) is much smaller in a 2 - 2 architecture than the equivalent gain in a 1 - 1 architecture and that makes the tracking jitter proportionally smaller.
The use of a ternary phase detector further reduces the peak tracking jitter [2].

This 2 - 2 loop tracks very well, as long as the loop filter and the VCO operate within their range of normal operation.

A unit step input generates an output with an initial step as high as the high frequency gain,
and a following ramp, with a slope equal to the high frequency gain times the cut-off frequency.

Loose-tracking conditions[edit]

When the phase detector outputs a constant request for higher, of for lower, frequency for a significant number of clock cycles ,
a temporary lack of bang-bang around the locking condition occurs, while the VCO lags behind a rising or falling input phase .

As this interval grows, the tracking error increases (see the linear ramp of the step response of the filter), and this might result into a phase error beyond the tolerance limit.

This 2 - 2 loop may drift away from lock more than the other type 1 loops, if the phase information is not refreshed, as indicated also by its linear model.

This may occur for two different causes:

  • the input signal has too few transitions (run-length problem, that can be approximately described using the stability factor ξ) or
  • the phase of the input signal varies too fast for the loop to track (slew-rate problem, that is investigated by simulations with sinusoidal input jitter close to the tolerance limit).

Both causes can reduce the tolerance of the CDR, and the effects of each can be reduced at the expenses of other CDR performances.

Run-length problem[edit]

The actual statistic of the transitions in the input signal is so difficult to predict that only a simple worst-case approach can be of use.

The very extreme case when transitions come periodically and separated by a constant number of line-pulse periods may give some insight and explain why large design margins are found in real monolithic CDRs.

In a condition of very rare but periodic transitions, the fundamental parameter is the time that the loop waits before the next update of the input phase, update that comes from the next transition of the input signal.

When a transition comes as soon as possible, the update time is: tupdate = 1/fp.
When a bit of the same sign follows in the input signal, tupdate at least doubles. More precisely:
tupdate = run-length * 1/fp.

It is convenient to define a parameter ξ:

ξ = 2 τz / tupdate

The longer the run length, the more critical the loop response may become . In fact, ξ is called the stability factor[3].

Let's focus now on what happens in the condition of bang-bang tracking.

The last bang corrects the filter output, higher or lower, by a jump of GφGf [v], and a ramp follows, in the same direction, with slope GφGf ωz [volt/sec]. (See the figure above).
The VCO frequency jumps GφGfGVCO = G [rad/sec] and then ramps with a slope of GφGfGVCOωz = Gωz [rad/sec2]
(GφGfGVCO = G, where the phase detector outputs can be -Gφ, +Gφ if the detector is binary and -Gφ, 0, +Gφ if it is ternary)
The quantity G is very closely related to the quantity fbb[4]. Both measure the frequency jump during bang-bang tracking, and are related by the formula G = 2π fbb.
While fbb is easy to interpret as the frequency jump and is fixed by the circuitry of the CDR, G is used as a nominal value for the open loop gain, in the nominal conditions of DT = 1 and maximum phase error (i.e. minimum Gφ). In fact, G is always found multiplied by DT in the formulae that describe the loop behaviour.

The VCO phase, as a function of the time t, is the sum of a linear ramp Gt plus a parabolic ramp \tfrac {1} {2}zt2 .

After tupdate, the VCO phase has increased (or decreased) by a linear part G tupdate [v] plus a parabolic part \tfrac {1} {2} G ωz tupdate2 [rad].
the ratio of the linear part of the phase increase to the parabolic part of the phase increase is exactly the stability factor ξ:
G tupdate / (\tfrac {1} {2} G ωz tupdate2) = 2τz / tupdate = ξ
When the update takes place, the new bang makes the filter output jump in the opposite direction by a step of Gf [v], followed by another ramp, now in this new direction.
In order to stay in tracking and not to sidetrack out of lock, the phase drift during tupdate must not make the VCO phase drift outside the lateral eye opening:
\tfrac {1} {2} G ωz tupdate2 + G tupdate < LEO (0 < LEO ≤ π)
\tfrac {1} {2} G ωz (2τz/ξ)2 + G (2τz/ξ) < LEO (0 < LEO ≤ π)
The equation yields always one positive real root[5]corresponding to ξ ≥ 2.

The value of G however decreases from its nominal value proportionally to the reduction of DT from its maximum of 100 %.

The ability of the CDR to tolerate with minimal phase drift some very long run-lengths, and/or periodic repetitions of them, can be increased increasing the value of τz at the design stage (ξ = 2τz / tupdate).

This reduces the bandwidth of the loop filter ωz and has the adverse effect of reducing the frequency lock-in range and of increasing the lock-in time.

In practice, values of ξ in excess of 1000, even with low transition densities as found in SONET transmissions, are not used.

Slew-rate problem[edit]

The 2 - 2 CDR is able to vary rapidly its frequency. If the input signal offers the maximum transition density, the loop can respond to an input phase step with a frequency step equal to G [rad/sec], i.e. with a phase ramp of slope G.

The value G (calculated with DT = 100%) represents the bang bang frequency step but also the reference loop gain ( Gφ is calculated with the largest phase input error, typically ±π , multiplied by DT, Gf is the value of the filter gain in the flat region, GVCO is a linear approximation around the fp working point ).

But if the phase of the input signal varies more rapidly than G rad/sec2, then a phase error appears and it may grow and possibly affect the CDR tolerance.

This problem may be investigated using a sinusoidal input phase jitter. This is also useful as the tolerance curve of the CDR is measured as a function of a sinusoidal input jitter.

A sinusoidal function (of time in the case of jitter) has its maximum rate of variation at the zero crossings, and its maximum rate of variation is the product of its amplitude by its angular frequency, Aω in the figure here below:

Time diagram of a sinusoid of angular frequency ω and amplitude A,
with emphasis on the maximum slope equal to Aω, that relates to the slew-rate concept

Maximum phase slew-rate = maximum frequency deviation.

The value of ωz is kept low in order to have a stability factor ξ large enough.

But ωz can not be too low, or else the slew rate (and the jitter tolerance limit!) at medium/low frequencies become too low as a consequence. (develop this point with comments and a figure)

There always exists the possibility that the VCO is not able to follow the rapidly changing phase of the input, because the rate of change of the VCO phase is insufficient. The VCO is "slew-rate" limited.

This is not normally due to late response of the VCO driven by the signal from the filter output.

The frequency deviation limits of the CDR are often set by the characteristics of the loop filter, rather than by the extremes of the frequency range of the VCO itself.
"The VCO is designed to respond fully in one update time. This is usually very easy to achieve in ring-oscillators and possible with some care using low-Q VCOs." [6]).

The slew-rate is originated by the loop filter that has a very limited gain (= an attenuation) at frequencies higher than ωz.

In fact, the Gf at high frequencies is kept as small as possible to reduce the "tracking" jitter due to the bang-bang jumps, but can not be reduced too much or else the "slew-rate" becomes excessively small.

External References[edit]

  1. a b C. Response to Phase Step
  2. Richard C.Walker article, A. Run-length and Latency, pg 10.
  3. Richard C.Walker article, A. Stability Factor, pg 4.
  4. Richard C.Walker article, p. 3.
  5. Roots of \tfrac {1} {2} G ωz (2τz/ξ)2 + G (2τz/ξ) - LEO = 0 are: 1/\xi =\tfrac{-1\pm\sqrt{1+\tfrac{2LEO}{G\tau_z}}} {2}.
  6. Richard C.Walker article, VII. C. VCO Tuning Bandwidth, pg 10.