# Clock and Data Recovery/Structures and types of CDRs/The CDR phase comparator

### The comparator shall detect the relative phase and the missing transition

A CDR phase comparator is a digital circuit operating at line speed that compares the transitions between different pulses of the received pulses and the transitions of the local clock.

It provides two outputs:

1. a signal, clocked by the local clock, that indicates whether a transition in the incoming line signal is present and tells whether the second signal is meaningful or not.
2. a signal, in the form of a pulse or of a couple of pulses, that tells the sign (bang-bang comparator) or the value (linear comparator) of the phase difference at its inputs

The same information can be translated into equivalent signals, depending:

• on the circuits that follow the phase comparator and
• on the architectural choice between replicating the previous detection when a transition is missing, or simply declaring the mid range, indifferent output value when the transition is missing.

In case of a missing transition between two subsequent line pulses;

• the comparator reconfirms the same phase detection of the previous clock period, or
• the comparator does not output any indication by generating a level corresponding to “no phase difference detected”.

The phase comparator output(s) are always subject to low-pass filtering so as to reduce the high frequency contents, that do not carry phase information but that can propagate as noise to other blocks of the CDR.

This low-pass (always present) rejects only signal frequencies higher that those that participate in the loop operation. It is the subsequent filter block -when present- that takes care of shaping the loop frequency responses.

Even if the comparator low-pass and the filter block are physically close and often combined together, it is useful to keep separate the two functions: a clear distinction will render the engineering tasks easier.

### The non-linearities of the phase comparator are the most critical for the CDR modeling

Mathematical models of a circuit can be very useful. This is especially true if the circuit operation can be considered as linear: in such case the mathematical terms are very neat and describe the circuit in all its different conditions.

Unfortunately the reality is never exactly linear. Rather, it is seldom very close to linear and sometimes can be markedly distant from linearity.

The phase comparator is the CDR component that deviates more often and to a larger extent from linearity.

### Inevitable non-linearities of the phase comparator (the "linear" phase comparator)

#### Linear range

Even if a circuit operates as linear (to any practical purpose), it has a finite range of operation. The EXOR circuit is probably the best introductory example:

The figure above represents a clock signal on the lower input that changes its delay with respect to the upper input. The output is a periodic signal of twice the frequency of the inputs (the EXOR is a “multiplier”). If such delay reaches one full half cycle of the period of the two signals (180o), the output reaches its maximum level. If the delay is further increased, then the output gradually decreases to its minimum level. If the two inputs are exactly in phase with each other (0o), the output is again at its minimum. If the phase difference is gradually varied, the entire input-output characteristic of this circuit can be obtained. It is a triangular sawtooth of period 180o (= π) and amplitude +/- π (or 0 to 1, depending on the circuit implementation!).

The useful signal is the filtered output, not the output of the EXOR, that has useless wide swings at the clock frequency. In fact the phase comparator always works at the bit line frequency (very high) but the CDR loop just needs the low frequency components of the phase comparison (Low frequency means in this case “not higher than the maximum frequency of significance for the control loop operation”, which is at least 10 times lower than the bit line frequency, but often 100 or more times lower). In the figure above, two points might be emphasized:

1. Only one of the two slopes of the sawtooth characteristic correspond to stable operation of the loop. Operation on the other one is unstable and the working point would quickly move to the closest end of the nearest stable slope.
2. The gain of this comparator, along any stable slope of its characteristic, is 1V / π/4 radian, that is 1.273 V/radian.

#### Uneven density of transitions in the reference signal

In a digital transmission, the incoming signal carries its phase information with its transitions from one level to another. The NRZ bit stream (the most often used for data transmission) has a variable density of transitions. (It is sometimes replaced by a coded signal, but the problem of variable density of signal transitions, although mitigated, remains). In a NRZ signal, a transition occurs when a bit 1 is followed by a bit 0, or viceversa.

Introduction to the NRZ-to-Clock phase comparator. See the next figure for the full circuit.

When a bit is followed by a bit of the same polarity, no transition occurs. The "run-length" is 2.

In the CDR jargon, generally run-length is the length of stretches (runs) of repeated bits during which the signal does not change.

The term transition density, DT, addresses the same concept from the steady state point of view.

With reference to a given length of a serial signal, and in the hypothesis that it is the average that matters :

DT = actual number of transitions / maximum amount of transition

#### the "linear" phase comparator

A very simple phase comparator generates a pulse every time a signal transition is received, like the EXOR multiplier of the previous section above does when comparing two clock signals.
That comparator (like the one in the figure above) is considered “linear” because the duration of the generated pulses is proportional to the phase distance between the transition of the incoming signal and the corresponding transition of the other signal that enters the other input of the comparator.
The pulses obtained in the figure above tell -with their duration- the phase distance between each transition of the incoming signal and the next sampling edge of the local clock (such distance should be 900 , or π/2, for optimum sampling of the received waveform).
Unfortunately such pulses can only be obtained when a signal transition is present.
What to do when no transition is received? This is similar to the dilemma of a car driver at night when temporarily dazzled by an excess of light.

• 1. To steer abruptly to one side? Certainly not! But this is what our waveform in the figure above would make our CDR do, because it stays at its lowest level when no transitions are present!
• 2. The driver could take the steering wheel to its center position whenever he can not see. The equivalent to taking the steering wheel to its mid position would be obtained with the retrofit to our phase comparator that is described in the following figure.
- In case of a transition, It subtracts a pulse lasting exactly one half-period to the pulse generated by the comparator. As a result, just the difference between zero phase and transition phase is the actual output.
- In case the transition is missing, the comparator contributes with a low level, and the retrofit with a high level: the actual output is a constant mid level, that corresponds to the detection of zero phase diference.
NRZ-to-Clock phase comparator
The compensating pulse starts from zero and goes negative as soon as the comparing pulse ends.
The (positive) comparing pulse has a duration proportional to the phase difference (o for -π, Tp for +π), while the (negative) compensating pulse has a fixed duration of Tp / 2.

50% clock duty cycle not necessary

The clock waveform needed by the linear comparator in the figure above must have a 50% duty cycle. The duration of the compensating pulse depends on it.
Is it possible to conceive another variant of the basic linear comparator, where this 50% duty cycle is not necessary? Yes!
E.g., the signal “Period following a transition” could be inverted and used as compensating pulse. It would directly drive the second resistor that should be doubled in value to compensate for the doubled duration of the compensating pulse.

A clock for a linear phase comparator does not need to be 50% duty cycle, because just its positive going transition is used to measure the relative phase.

The gain of this phase comparator will be a function of the ratio between the actual number of transitions in the incoming signal, and the number of transitions corresponding to a continuous 10101010.. data pattern in it. Let's call this ratio DT, which will vary between 0 and 1.
The comparator gain can be calculated considering that the couple of output pulses corresponding to one input transition yield:
- 0.25 V for a clock sampling the transition (clock phase = 0 radian),
- 0.5 V for a clock sampling the center of the received pulse (clock phase = π radian) and
- 0.75 V for a clock sampling the end transition of the received pulse (clock phase = 2π radian)
For sake of convenience the signal range is mapped from 0.25..0,75 to 0..1.
Taking into account also the transition density:
Gain = DT / 2π [V/radian.]
The characteristic of this comparator as a function of the phase difference of its inputs is again a sawtooth, but, in this case, with normally oblique stable slopes and vertical unstable slopes.
Characteristic of the phase comparator (the transition density of the incoming signal is assumed to be 100%)

It is important to point out that the transition density DT in practical cases is never very close to zero. The information bits sent to the other end of the communication link are processed and receive the addition of other bits. When transmitted they become, amongst other elaborations,:
often structured in bytes via the 8B10B coding (which ensures that the difference between the count of 1s and 0s in a string of at least 20 bits is no more than 2, and that there are not more than five 1s or 0s in a row. See also 8b/10b encoding, from Wikipedia, the free encyclopedia)
intermixed with headers and tails of layer 1, layer 2 and layer 3 framing
so that the bit flow that is actually transmitted exhibits a DT much closer to its mid range value of 0.5. The values of DT actually expected shall be used to evaluate the actual behavior of the phase comparator and its gain.
• 3. It would be best for our driver -temporarily blind- to maintain for a while the position of the steering wheel that he had just before the loss of vision. The same holds good for the output of our phase comparator. But our phase comparator operates at the line bit frequency, and its memory span can not be extended beyond a few flip-flops, that is not beyond a few periods of the local clock. After that, any memory of the last meaningful phase comparison is lost by the phase comparator. To find inside our CDR a memory element similar to the memory of our driver, we must involve the loop filter, and use it to maintain memory of the last meaningful information from the phase comparator. But if the blindness (=the lack of transitions) persists beyond a certain time, our unfortunate driver should not insist keeping the steering wheel turned, but shall gradually take it back to its central position. With a strong analogy, we shall not make our filter too rigid ( = too much of a low pass ), but allow it to evolve towards its discharged state (= towards driving the local oscillator to its free running frequency). In this latter sense, an elegant solution to the need of mitigating the problem (of uneven density of transitions in the received signal) can be seen in [1]. (A sub-circuit detects when a transition is missing in the incoming NRZ data stream [i.e. when the next data bit is NOT the opposite of the previous data bit]. In such occasions the output of the phase comparator would be unable to generate the couple of pulses whose average duration tells the phase difference between the local clock and the data transitions. The sub-circuit then forces the Low Pass Filter of the PLL to the same filter output that would result from the addition of a “dummy” couple of pulses equal to the last one from the output of the phase comparator.)

The circuit diagrams of the linear comparator in the figures above are reduced to the simplest case that still incorporates the essential features, for sake of quick understanding.
The actual circuits may be somewhat more complex, but retain the same essential structure and features.
A fundamental Hogge article[2] is always referred to when describing the linear phase comparator in the technical literature of CDRs.

### Deliberately non-linear phase comparator (bang-bang)

A popular choice amongst designers is the so called “bang-bang phase detector”.
Its characteristics are well described in the fundamental article of J.D.H. Alexander [3]
It is a circuit easy to understand and easy to design.
Unfortunately it is strongly nonlinear:

• its operations consists in the generation of pulses of fixed amplitude and duration at every period of the local clock, and
• it detects only the sign of the phase difference but does not collect any information about the amount of the phase difference it detects.

The term detector is more appropriate in this case than the term comparator.
The bang-bang detector is in general easy to integrate. Sometimes (when the line pulses are at frequency close to the Ft of the technology [4]) it may even be the only possible comparator for a monolythic CDR.

#### The classic bang-bang phase detector

The bang-bang phase detector compares the negative edge of the clock with the data transition,
and the present data bit with the previous data bit.
Using 4 flip flops the resulting info is contemporarily available for one entire clock period.

The flip flop 3 is clocked with the negative edge of the local clock. This flip flop detects (when there is an transition in the input data) whether its sampling edge comes before (= Early) or after (= late) the transition in the incoming data.
The other three flip flops are clocked with the positive edge of the local clock, and make their outputs stable and contemporarily available for one entire clock period:

• Q1 : the result of sampling the input data waveform with the positive edge of the local clock;
• Q2 : the result of sampling the input data waveform, with the positive edge of the local clock, one clock period before;
• Q4 :
• the clock negative edge has been early (E=1) or late (E=0) with respect to the data transtion, if a transition has occurred;
• if no transition has actually occurred, Q4 tells the sign common to the two bits (but in this case, this signal is not relevant for phase detection).

It should be noted that this comparator requires a local clock with positive and negative edge equally spaced by half a clock period (duty cycle = 50% ).

This distance in time between the negative edge and the positive edge represent the time between the transition detection and the sampling of the received pulse.
If it is different from 50% of the clock period, then the sampling will deviate correspondingly from the optimum sampling instant, when the received pulse (supposed symmetric) is maximum, and the Bit Error Rate will worsen.

The output of the detector is made by the three signals, Q1, Q2 and Q4, but can essentially be resumed by two bits: T and E. 1. T = there has been, or there has not been, a transition in the input signal. T = Q1Q2 + Q1Q2 2. E = if there has been a transition, the local clock has been found either early or late.

Detector logic: which outputs are used depends on the type of loop filter
$Q_1$ $Q_2$ $Q_4$ $T$ $E$ ${\color{blue}\overline{UP}=\overline{T}+E}$ $DOWN=T*E$
0 0 0 0 0 1 0
0 0 1 0 1 1 0
0 1 1 1 0 0 0
0 1 0 1 1 1 1
1 1 0 0 1 1 0
1 1 1 0 0 1 0
1 0 1 1 1 1 1
1 0 0 1 0 0 0

Note that E is meaningless when T=0 (cells with light grey background), that is when no transition of data occurs.
The logic after the flip flops can be slightly modified if a charge pump is present, and generate the two signals UP and DOWN to drive the two current generators of the charge pump.

Reconfirm the previous detection when a transition is missing?

It is possible to add to the detector logic some circuits that channel into one wire only the information needed to drive a subsequent analog stage (amplifier/filter).
During the clock period corresponding to a missing transition, it is possible either:

• to generate a waveform of average value ½ (in the example of the temporarily blind driver, this corresponds to bringing the steering wheel to its central position). This is exactly equivalent to what the two signals UP and DOWN do in the case of the charge pump, that outputs a zero current for one clock period in correspondence to a missing transition;
• to repeat the last output, again and again as long as no new transition arrives (in the example of the temporarily blind driver, this corresponds to holding the steering wheel in its present position, until sight returns).

The additional logic would conceptually work as in the following figure:

Bang bang output on a single wire, without or with transition stuffing

(Choosing either option is less important than in the case of a linear comparator, because of the inherently high gain of the bang-bang detector.)
The option of reconfirming the previous detection in case of lack of transitions offers the advantage of a faster acquisition (when far from lock, the bang-bang gain is low) and the disadvantage of an increased jitter once acquisition is achieved (when the bang-bang gain is very high).
A fast acquisition is fundamental in burst-mode transmission, where unfortunately the advantage cannot be appreciated. In fact there is no need to reconfirm because transitions are not missing! The protocols include at the beginning of every burst a sequence of dummy bits with transition density = 1, for a duration sufficient for a good acquisition. As the advantage cannot materialize, the repetition would only bring disadvantages, and is not implemented in burst mode.
In the case of continuous mode transmission, a fast acquisition is not the prime requirement and the addition of jitter to the input signal is avoided.
The bang-bang detector already generates a lot of jitter anyway, and a further jitter addition is not welcome.

As the advantage is not appreciated much and the disadvantage is negatively perceived, the repetition is not implemented in continuous mode either.

### The charge pump inside a PLL comparator for clock and data recovery

The two output signals of the comparator logic, (for instance T and E), are combined together. A simple low-pass follows. The resulting signal drives the subsequent block (amplifier/filter).
In most monolythic implementations of CDRs, the two output signals, coming out of the sequential logic of the phase comparator, drive a charge pump.[5]
On each wire, pulses of fixed amplitude come from the comparator logic with the frequency of the local oscillator (equal to fp when in lock).
They represent with their value 0 or 1 (and with their duration in a linear Phase Comparator) the relative phase of the input data signal with respect to the local clock.

Charge pump that follows the comparator logic.
Possible loop filters (in green and red respectively for the type 2 and type 1 loops of 2nd order).
The capacitor C (in black) is the charge pump low pass.

The active part of the charge pump is made by two current generators of equal value.
One is a source from Vdd and the other is a sink to Vss; their outputs are connected.
The source is activated when the comparator logic indicates that the second input of the comparator (the local clock in a PLL) is late with respect to the first input (the incoming data stream in a PLL).
The sink is activated when the comparator logic indicates Early.
If both, or neither, are active at the same time, it means no indication of phase difference, neither of early clock nor of late clock.
The output node, connected to the two current generators, drives in turn an RC network that filters the current pulses. More precisely, the RC network accomplishes two functions:

1. to smooth down the sharp corners of the current pulses, eliminating the high frequency components around fp, 3fp, etc... This low-pass does not eliminates baseband signal frequencies that carry useful phase information from the comparator (in the figure above, this function is performed essentially by C).
2. to filter the control loop signals so that the dynamic performances of the loop (jitter transfer, jitter tolerance, noise generation) are modified and improved (in the figure above, this function is primarily performed by the colored RC networks).

The filtering network in green in the figure is in actuality the most common, and implements a 2nd order type 2 loop. If the network in red is used instead of the green one, a 2nd order type 1 loop is obtained.

### Gain of the two main types of phase comparators

The gain of the bang-bang detector is not constant, but varies with the signal amplitude.
The gain is maximum when the difference signal at the input of the detector deviates least from its center value (from zero difference).

The gain is minimum instead when the signal deviates most from its center value.

When the gain of a bang-bang phase detector is indicated by a fixed value, that value means the minimum gain at the largest phase difference close to the output inversion.

Transfer curve and gain of the linear and of the bang-bang comparators as a function of the phase difference at their inputs

It is important to emphasize that the “instantaneous” gain of a bang-bang phase detector in a CDR has a non zero but extremely low probability to reach the highest values of the its static characteristics, because the jitter present in the incoming signal is never exactly zero at the signal level transition.

Even when acquisition is achieved, some input jitter is present and the output of the phase detector jitters along the high slopes of the characteristic curve, from left to right and back, but cannot settle at the very top (which may happens only if the jitter was constantly exactly = 0).

### References

1. A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit Using the Sample -and-Hold Technique by Noboru Ishihara and Yukio Akazawa, IEEE Journal of Solid-State Circuits, vol. SC-29, pp. 1566-1571, December 1994
2. Hogge, C., “A Self Correcting Clock Recovery Circuit,”. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-32, NO. 12, DECEMBER 1985, pp. 2704-2706.
3. J.D.H. Alexander, "Clock Recovery from Random Binary Signals", vol. 11, pp. 541 - 542, October 1975 in Electronics Letters. © Institution of Electrical Engineers.
4. Richard C. Walker (2003). "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7.
5. Floyd M. Gardner, "Charge-Pump Phase-Lock Loops", vol. COM-28, NO.11, pp. 1849 - 1858, November 1980 in IEEE TRANSACTION ON COMMUNICATION.