Clock and Data Recovery/Structures and types of CDRs/The CDR phase comparator

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The comparator shall detect the relative phase and the missing transition[edit]

A CDR phase comparator is a digital circuit operating at line speed that compares the instants of transition (between different levels, or different phases) of the received pulses with the instants of transition of the local clock.

It provides two pieces of information, updated at every cycle of the local clock:

  1. whether a transition in the incoming line signal is present, i.e. whether a meaningful comparison can be made;
  2. in the form of a pulse or of a couple of pulses, just the sign (bang-bang comparator), or the value with sign (linear comparator), of the phase difference at its inputs.
The same information can be translated into equivalent signals, depending:
  • on the circuits that follow the phase comparator and
  • on the architectural choice about what to do when a signal transition is missing:
  • simply declaring the mid range, indifferent output value when the transition is missing, or
  • replicating the result of the previous detection when a transition is missing.
As explained further on in this page, the first option (=mid range output on no transition) is often used for bang-bang detectors (Ternary detectors [1]), while the second option (reconfirm last detection on no transition) can be found in some linear phase comparators and in bang-bang detectors as well.


The phase comparator output(s) are always subject to low-pass filtering to reduce the high frequency contents, that do not carry phase information but that can propagate as noise to other blocks of the CDR.

This low-pass (always present) rejects only signal frequencies higher that those that participate in the loop operation. It is the subsequent filter block -when present- that takes care of shaping the loop frequency responses.


Even if the comparator low-pass and the filter block are physically close and often combined together, it is useful to keep separate the two functions: a clear distinction renders the engineering tasks easier.


Variable density of transitions in the incoming signal[edit]

In a digital transmission, the incoming signal carries its phase information by its transitions from one level to another.

The NRZ bit stream (the most often used for data transmission) has a variable density of transitions. (An encoded signal may be used, but the problem of variable density of signal transitions, although mitigated, remains).

In a NRZ signal, a transition occurs when a bit 1 is followed by a bit 0, or viceversa.


Irregular flow of incoming level transitions[edit]

The irregularity can be approximately described defining two parameters of the NRZ bit stream:

- the maximum run length (the number of contiguous bit (runs) during which the signal does not change level);
- the transition density DT (average probability of a signal level change between adjacent pulses of the signal), that corresponds to the concept of the run-length, but from the long-term average point of view. With reference to a given length of a serial signal, and in the hypothesis that it is the average that matters :
DT = actual number of transitions / maximum amount of transition [0% to 100%]

Both parameters depend on the NRZ bit stream itself and on the rules used to process it. Essentially, these rules are either:

a change of the bits, according to a fixed rule that changes each bit taking into consideration it and a limited number of preceding bits, called scrambling
an encoding that increases by some percent the bit rate of the original bit stream, either
- FEC, or
- line codes. The most important line codes are presented in the following table.

The maximum run-length for a code is easy to identify for the codes created to allow a good clock recovery.

 Code  Max run-length   Transition density  Notes
Classic old SONET systems 80 bit time intervals 50 % average framing bits and scrambling of payload
64/66 65 bit time intervals 50 % average 2 framing bits and scrambling of payload;1900 years @ 10 Gbps
8B10B 5 bit time intervals 30% min, 80% max running disparity max 2


With a rough approximation, the run-lengrth may affect the closed loop performance of the CDR in proportion to its value multiplied by: 1 / (fp - ffr ).

Depending on the specific CDR implementation, the jitter generation may be the performance more affected, or the jitter transfer, or the jitter tolerance.

In any case, the minimum and maximum values of DT that are specified for the application considered, do influence significantly both the design and the testing of a CDR.


What to do when a transition is missing?[edit]

The phase comparator renders available phase information when (i.e. if during one period of the local clock) a transition is received, and a the missing transition information when (i.e. if during one period of the local clock) no transition has been present in the received signal.

How is such information supplied to the next circuit block (the amplifier/filter) ? What use is made of it?

The answers depend on how the overall PLL circuit is made (i.e. on its architecture) and on what the PLL circuit is meant to do (on its application).


A first distinction can be made between two alternatives:

  1. hold, in the sense of prolonging the current PLL state
  2. free-running, in the sense that the phase comparator output becomes mid-range for that clock cycle. If maintained, this output of the PD would make the local oscillator run free at its "free-running" frequency.
This is similar to the dilemma of a helmsman at night when temporarily unable to see the lighthouse he should guide the ship to, because dazzled by a flash of light, or because something is passing in front, or…
  1. The helmsman could take the helm to its amidships position whenever he can not see (= free-running).
  2. The helmsman could otherwise hold the position of the helm that he had just before the loss of vision. It should be kept in mind that the phase comparator operates synchronously at the line bit frequency, and its memory span can not be extended in time: at the next clock edge that triggers the flip flops, all memory of the previous phase comparison is lost. To find inside the CDR a memory element similar to the memory of our helmsman, the analogy must include also the loop filter (its time constant -in many cases of the order of 1000 pulses [2] - is longer than the longest lack of transitions -that never exceeds 100 pulses (see the Table above)-) and use it to remember the last meaningful information from the phase comparator.
This second analogy involves not only helmsman and helm, but also the complete steering gear from helm to rudder, the integration from the rudder position to the direction that the ships points to, and the overall inertia of the ship.
The helmsman corresponds to the detection of the phase error, the steering gear to the amplifier/filter block, the integration to the phase to frequency relationship in the VCO and the overall inertia to the PLL closed loop low pass characteristic.


The choice amongst 1. and 2. can only be made taking into consideration the ship characteristics and function, which correspond to taking into consideration the CDR architecture and application.

In a small ship with little inertia and direct connection of the tiller to the rudder (PLL architecture 1-1), solution 2. is the best choice . And if the ship is towed, the free-running position is the destination implicit in the towline, very much like the local clock in the case of a phase aligner.
In a very fast, extremely manoeuvrable ship with short hull and very wide rudder angles, that needs fast control and overcompensation, it is only the good reaction of the helmsman and of a servo transmission that can achieve the correct performance. Solution 1. or 2.apply. Here an analogy with 2-2 architectures inside monolithic CDRs for fiber optic receivers is apparent.
In a big liner with refined mechanics and well balanced hull, 2. may look like a good solution. But a CDR that has reached phase lock looks like a ship that is constantly driven with some offset of the rudder from its central position. The measure of this biased drive is the difference between the free running frequency of the local oscillator ffr (i.e. the center amidship position of the helm) and the frequency of the received pulses fp (the rudder position that keeps the ship pointed towards the lighthouse; the offset from center of the rudder position is analog to of the steady state drive error of the VCO). If cost is not a big concern, then 1. is the good solution. That means to disconnect the helm and to freeze the rudder position. On the PLL side of the analogy, a fundamental part of the control loop, the amplifier/filter, must be involved in the solution. This is the case of CDRs with 2-1 architecture for long regeneration spans in Telecom applications. An implementation of the solution 1. can be found in [4]. (A sub-circuit detects when a transition is missing in the incoming NRZ data stream [i.e. when the next data bit is NOT the opposite of the previous data bit]. In such occasions the output of the phase comparator would be unable to generate the couple of pulses whose average duration tells the phase difference between the local clock and the data transitions. The sub-circuit then forces the Low Pass Filter of the PLL to the same filter output that would result from the addition of a “dummy” couple of pulses equal to the last one from the output of the phase comparator.) A further refinement of this type of retrofit is found in [5].


The non-linearities of the phase comparator are the most critical for the CDR modeling[edit]

Mathematical models of a circuit can be very useful. This is especially true if the circuit operation can be considered as linear: in such case the mathematical terms are very neat and describe the circuit in all its different conditions.

Unfortunately the reality is never exactly linear. Rather, it is seldom very close to linear and sometimes can be markedly distant from linearity.

The phase comparator is the CDR component that deviates more often and to a larger extent from linearity.


Inevitable non-linearities of the phase comparator (the "linear" phase comparator)[edit]

Linear range[edit]

Even if a circuit operates as linear (to any practical purpose), it has a finite range of operation. The EXOR circuit can be a good introductory example:

Exor phase comparator.png

The figure above represents a clock signal on the lower input that changes its delay with respect to the upper input.

The output is a periodic signal of twice the frequency of the inputs (the EXOR is a “multiplier”).

If such delay reaches one full half cycle of the period of the two signals (180o), the output reaches its maximum level.

If the delay is further increased, then the output gradually decreases to its minimum level.

If the two inputs are exactly in phase with each other (0o), the output is again at its minimum. If the phase difference is gradually varied, the entire input-output characteristic of this circuit can be obtained. It is a triangular sawtooth of period 180o (= π) and amplitude +/- π (or 0 to 1, depending on the circuit implementation!).

Exor phase comparator of clocks.png

The useful signal is the filtered output, not the output of the EXOR, that has useless wide swings at the clock frequency. In fact the phase comparator always works at the bit line frequency (very high) but the CDR loop just needs the low frequency components of the phase comparison.

(Low frequency means in this case “not higher than the maximum frequency of significance for the control loop operation”, which is at least 10 times lower than the bit line frequency, but often 100 or more times lower).

In the figure above, two points should be noted:

  1. Only one of the two slopes of the sawtooth characteristic correspond to stable operation of the loop. Operation on the other one is unstable and the working point would quickly move to the closest end of the nearest stable slope.
  2. The gain of this comparator, along any stable slope of its characteristic, is 1V / π/4 radian, that is 1.273 V/radian.


The "linear" phase comparator[edit]

A very simple phase comparator generates a pulse every time a signal transition is received, like the EXOR multiplier of the previous section above does when comparing two clock signals.

Exor and FF comparator for NRZ data.png
Introduction to the NRZ-to-Clock linear phase comparator. See the next figure for the full circuit.

This type of comparator is called “linear” because the duration of the generated pulses is proportional (=linear relation) to the phase distance between the transition of the incoming signal and the corresponding transition of the other input signal.

The pulses obtained in the figure above tell -with their duration- the phase distance between each transition of the incoming signal and the next sampling edge of the local clock (such distance should be 900 , or π/2, for optimum sampling of the received waveform).

Unfortunately such pulses can only be obtained when a signal transition is present.


What should the linear comparator do when a transition is missing?[edit]
  • 1. To steer abruptly to one side? Certainly not this type of linear comparator! (Some bang-bang comparators may, in special cases). But this is what the output waveform in the figure above does, because it stays at its lowest level when no transitions are present!
  • 2. The helmsman could take the helm to its amidships position whenever he can not see. The equivalent to taking the helm to its central position would be obtained with the retrofit to our phase comparator that is described in the following figure.
- In case of a transition, It subtracts a pulse lasting exactly one half-period to the pulse generated by the comparator. As a result, just the difference between zero phase and transition phase is the actual output.
- In case the transition is missing, the comparator contributes with a low level, and the retrofit with a high level: the actual output is a constant mid level, that corresponds to the detection of zero phase diference.
Linear phase comparator for NRZ data input var gain.png
NRZ-to-Clock phase comparator
The compensating pulse starts from zero and goes negative as soon as the comparing pulse ends.
The (positive) comparing pulse has a duration proportional to the phase difference plus Tp / 2 (0 for -π, Tp for +π), while the (negative) compensating pulse has a fixed duration of Tp / 2.
50% clock duty cycle is not necessary in a linear phase comparator
The clock waveform needed by the linear comparator in the figure above must have a 50% duty cycle. The duration of the compensating pulse varies with it.
Is it possible to conceive another variant of the basic linear comparator, where this 50% duty cycle is not necessary? Yes!
E.g., the signal “Period following a transition” could be inverted and used as compensating pulse. It would directly drive the second resistor that should be doubled to compensate for the doubled duration of the compensating pulse.
A clock for a linear phase comparator needs not be 50% duty cycle, because just its positive going transition is really needed to measure the relative phase.
The gain of this phase comparator will be a function of the ratio between the actual number of transitions in the incoming signal, and the number of transitions corresponding to a continuous 10101010.. data pattern. This ratio is DT, the transition density, defined earlier in this page.
The comparator gain can be calculated considering that the couple of output pulses (corresponding to one input transition) averages:
-50% for a clock sampling the transition at the beginning of the received pulse (clock phase = -π radian),
0% for a clock sampling the center of the received pulse (clock phase = 0 radian) and
+50% for a clock sampling the end transition of the received pulse (clock phase = +π radian)
Taking into account also the transition density:
Gain = DT / 2π [V/radian.]


The characteristic of this comparator as a function of the phase difference of its inputs is again a sawtooth, but has normally oblique stable slopes and vertical unstable slopes.
Characteristic of the linear comparator. Sawtooth with linear, stable slopes and vertical, unstable slopes alternating. Three different densities of the level transitions that can be compared with the reference clock.
The transition density DT in practical cases is never very close to zero. The information bits sent to the other end of the communication link are processed and receive the addition of other bits. When transmitted they become, amongst other elaborations,:
- often structured in bytes via the 8B10B coding (which ensures that the difference between the count of 1s and 0s in a string of at least 20 bits is no more than 2, and that there are not more than five 1s or 0s in a row. See also 8b/10b encoding, from Wikipedia, the free encyclopedia)
- often scrambled (which is exactly meant to reduce the probability of long strings of identical bits.| See also Scrambler in telecommunication and recording, from Wikipedia, the free encyclopedia)
- often processed with Forward Error Correction coding ( | See also Scrambler, from Wikipedia, the free encyclopedia ).
- sometimes (Wide Area Networks) intermixed with headers and tails of layer 1, layer 2 and layer 3 framing
so that the bit flow that is actually transmitted exhibits a DT much closer to its mid range value of 0.5. The values of DT actually expected shall be used to evaluate the actual behavior of the phase comparator and its gain.


  • 3. It would be best for our helmsman -temporarily blind- to maintain for a while the position of the helm that he had just before the loss of vision. The same holds good for the output of the phase comparator if it is followed by a filter that can remember its present output for longer than the longest run rate expected. Note that the analogy is now between the rudder position and the signal that drives the VCO (= the output of the filter, not any longer simply the output of the phase comparator).

A CDR that has reached phase lock looks like a ship that is forever on a curving path. The measure of this unending curve is the difference between the free running frequency of the local oscillator ffr (i.e. the center position of the rudder) and the frequency of the received pulses fp (the difference telling the rotation of the rudder, analogy of the steady state drive error of the local oscillator). Therefore CDRs with linear comparators are least sensitive to long run-lenths when retrofitted in this sense. An implementation of such a retrofit can be found in [3]. (A sub-circuit detects when a transition is missing in the incoming NRZ data stream [i.e. when the next data bit is NOT the opposite of the previous data bit]. In such occasions the output of the phase comparator would be unable to generate the couple of pulses whose average duration tells the phase difference between the local clock and the data transitions. The sub-circuit then forces the Low Pass Filter of the PLL to the same filter output that would result from the addition of a “dummy” couple of pulses equal to the last one from the output of the phase comparator.). A further refinement of this type of retrofit is found in [4].

This 3. way of filling the intervals of lack of transition(s) uses some sort of "analog" memory and makes the gain of the linear comparator independent from the transition density and equal to its at maximum value DT.

The circuit diagrams of the linear comparator in the figures above have been reduced to very simple cases that still incorporate the essential features, for sake of quick understanding.
The actual circuits may be somewhat more complex, but they do retain the same essential structure and features.

A fundamental Hogge article[5] is always referred to when describing the linear phase comparator in the technical literature of CDRs.

The linear phase comparator as presented by Charles R. Hogge in its classic article of December 1985



Deliberately non-linear phase comparator (bang-bang)[edit]

Its characteristics are well described in the fundamental article of J.D.H. Alexander [6]

It is a circuit easy to understand and easy to design.

Unfortunately it is strongly nonlinear:

  • its operations consists in the generation of pulses of fixed amplitude and duration at every period of the local clock, and
  • it detects only the sign of the phase difference but does not collect any information about the amount of the phase difference it detects.

The term detector seems more appropriate than the term comparator in this case.

The bang-bang detector is easy to integrate inside a monolithic chip. Sometimes (when the line pulses are at frequency close to the Ft of the chip technology [1]) it may even be the only possible comparator for a monolythic CDR.



The classic bang-bang phase detector[edit]

The Alexander[6] phase detector
The bang-bang phase detector compares the negative edge of the clock with the data transition,
and the present data bit with the previous data bit.
Using 4 flip flops the resulting info is contemporarily available for one entire clock period.

The flip flop 3 is clocked with the negative edge of the local clock and detects (when there is an transition in the input data) whether its sampling edge comes before ( Early ) or after ( Late ) the data transition.

The other three flip flops are clocked with the positive edge of the local clock, and make their outputs stable and contemporarily available for one entire clock period:

  • Q1 : the result of sampling the input data waveform with the positive edge of the local clock;
  • Q2 : the result of sampling the input data waveform, with the positive edge of the local clock, one clock period before;
  • Q4 :
      • the clock negative edge has been early (E=1) or late (E=0) with respect to the data transtion, if a transition has occurred;
      • if no transition has actually occurred, Q4 tells the sign common to the two bits (but in this case, this signal is not relevant for phase detection).
This comparator requires a local clock with positive and negative edge equally spaced by half a clock period (duty cycle = 50%)
The distance in time between the negative edge and the positive edge represents the time between the transition detection and the sampling of the received pulse.
If it is different from 50% of the clock period, then the sampling deviates correspondingly from the optimum sampling instant when the received pulse (supposed symmetric) is maximum, and makes the Bit Error Rate worsen.
"Using a fully differential ring oscillator, it is possible to achieve a very precise 50% duty-cycle clock source."[1]

The output of the detector is a combinatorial function of the three signals, Q1, Q2 and Q4, but can essentially be resumed by two bits: T and E.

  1. T = there has been, or there has not been, a transition in the input signal. T = Q1Q2 + Q1Q2
  2. E = if there has been a transition, the local clock has been found either early or late. E = Q2Q4 + Q2Q4
Detector logic: different outputs for different loop filters: case of a charge pump
Q1 Q2 Q4 T E UP = T+E DOWN = T*E
0 0 0 0 0 1 0
0 0 1 0 1 1 0
0 1 1 1 0 0 0
0 1 0 1 1 1 1
1 1 0 0 1 1 0
1 1 1 0 0 1 0
1 0 1 1 1 1 1
1 0 0 1 0 0 0

Note that E is meaningless when T=0 (cells with light grey background), that is when no transition of data occurs.

The logic after the flip flops can be slightly modified if a charge pump is present, and generate the two signals UP and DOWN to drive the two current generators of the charge pump.

DOWN=T*E activates the charge pump (to reduce the cumulated charge) only when its value is 1. It is never 1 when T=0.
UP (= UP active low) activates the charge pump (to increase the cumulated charge) only when its value is 0. It is never 0 when T=0.


Reconfirm the previous detection when a transition is missing? More jitter but gain independence from DT ![edit]

It is possible to add to the bang-bang detector logic some circuits that channel into a single wire the information needed to drive the following stage in the PLL (the amplifier/filter).

This may be convenient in particular when the output signals from two different phase detector are put together to implement a Phase and Frequency Detector PFD.


During the clock period corresponding to a missing transition, it is possible for the detector to either:

  • signal free-running, i.e. to generate a waveform of average value ½ (in the example of the temporarily blind helmsman, this corresponds to bringing the helm to its central position).
This is exactly equivalent to what the two signals UP and DOWN do in the case of the charge pump, that output a zero current for one clock period in correspondence to a missing transition;
The detector that outputs an intermediate state, or level, when no transition is detected is called "ternary", as opposed to "binary" that can only output two states (or levels). A ternary detector is often found in practice.
The third level gradually propagates to the output of the charge-pump filter and then to the output phase of the VCO.
It is also possible to retrofit wit a sample-and-hold fixture the loop filter (between the first coarse low-pass at the output of the charge pump and the low-pass that actually implements the loop filter, in a way essentially identical to the continuous mode CDR using a linear comparator. The transition from the present level of VCO drive level to the free-running drive level can be made even longer.
  • signal hold, i.e. to repeat the last output, again and again as long as no new transition arrives. This is different from the hold of a linear comparator, that requires an additional analog memory. The bang-bang detector can easily be retrofitted to hold, but only into either of the two extreme output levels.
In applications with the 2 - 2 architecture this is mitigated by the very low gain of the filter block at mid and high frequencies, compensating the very high gain of the monolithic VCO.

The additional logic would conceptually work as in the following figure:

Bang bang output on a single wire, without or with transition stuffing


Which between free-running and hold? The question is best answered making reference to the CDR functions and applications.

  1. burst-mode CDRs and phase aligners in particular. Transition stuffing is NOT needed, and free-running is best.
To "reconfirm" the detector would always output the detection obtained from the last signal transition, independently of the number of cycles elapsed after it (independently of the instantaneous run-length).
The option of reconfirming the previous detection in case of lack of transitions would offer the advantage of a faster acquisition and the disadvantage of an increased jitter once acquisition is achieved.
A fast acquisition is fundamental in burst-mode transmission, where unfortunately the described advantage does not materialise. In fact there is no need to reconfirm because transitions are not missing! The protocols include at the beginning of every burst a sequence of dummy bits with transition density equal to 100%, for a duration sufficient for a good acquisition. As the advantage cannot materialize, the repetition is not a necessary choice in burst mode.
Phase-aligners are a special case of burst-mode CDRs, where the phase of the local clock does not drift at all unless explicitly requested to do so. Once acquisition is achieved, the phase bangs forth and back around the best position. No transition stuffing, as its only result would be to increase the jitter and to decrease the jitter tolerance. A ternary detector drives directly the phase of the local clock.


  1. In the case of continuous mode transmission, a fast acquisition is not the prime requirement and the addition of "hunting" jitter to the output signal is somewhat of a deterioration of performances. The bang-bang detector already generates a lot of jitter anyway, and a further jitter addition is not welcome.
Although usable for tightly constrained block codes as 8b10b, binary phase detectors are essentially unusable for codes such as 10Gb Ethernet 64b66b or SONET which have very long run lengths of up to 66 or 80 bits, respectively.[1]

On the other hand the repetition offers "the advantage of a constant detector gain and therefore of a reduced pattern dependent jitter"[7].

The the trade-off between advantages and disadvantages is debatable, but free-running in the sense of a ternary output is more often preferred also for continuous mode applications.


Bang-bang Phase Detector with “hold”[edit]

This detector is similar to the Alexander detector, from which it differs because its output that is made up of one wire only.

Description of a bang-bang PD with one output wire only.
The output remains at the previous level every time that the input data stream lacks a transition (i.e. it "holds"), and makes the detector gain independent from DT.

The data retimed by CK are present on Q1. They are then used to sample Q2:

  • with the leading edges in flip-flop 3 (the output used is Q3) and
  • with the trailing edges in flip-flop 4 (the output used is Q4).

Q3 and Q4 are obtained from the Q2 signal, that is sampled respectively by the leading edge and by the trailing edge of Q1 ( = by the transitions of the retimed data ).

Q3 stores the result of sampling the latest rising data transition by CK, Q4 stores the result of sampling the latest falling data transition by CK.

The multiplexer at the end is driven by the retimed data and uses Q3 or Q4 according to the retimed data polarity.

The PD output corresponds to asserting L with_hold_if T where L means Late_active_high and T means Transition_active_low.


The result is that the state machine output (= PD) is clocked by the local clock (CK in the figure above).


An equivalent representation of this PD, oriented to implementations inside high speed ICs, is presented in the next page.


The charge pump inside a PLL comparator for clock and data recovery[edit]

The two output signals of the comparator logic, (for instance T and E), are combined together. A simple low-pass follows. The resulting signal drives the subsequent amplifier/filter block.

In most monolythic implementations of CDRs, the two output signals, coming out of the sequential logic of the phase comparator, drive a charge pump.[8]

On each wire, pulses of fixed amplitude and duration come from the comparator logic with the frequency of the local oscillator (equal to fp when in lock).

They represent, with their value 0 or 1, the relative phase of the input data signal with respect to the local clock. (Their duration, unlike in a linear Phase Comparator, does not carry any "analog" information about the value of the input phase difference).

Charge pump that follows the comparator logic.
Both the green and red network implement a 2nd order, type 2 loop.
The red one makes the filter h-f gain (largely) independent from Ip
The capacitor C (in black) is the charge pump high-frequency low pass.

The active part of the charge pump is made by two current generators of equal value.

One is a source from Vdd and the other is a sink to Vss; their outputs are connected.

The source is activated when the comparator logic indicates that there has been a transition and that the second input of the comparator (the local clock in a PLL) is late with respect to the first input (the incoming data stream in a PLL).

The sink is activated when the comparator logic indicates that there has been a transition and that the local clock has been found early.


The condition when both are active, or are not active, at the same time, is equivalent to the third state of a ternary comparator and carries no indication of phase difference, neither of early clock nor of late clock.

The loop filter (in red or in green in the figure above) remains frozen and keeps the VCO frequency frozen as well.

The output node, connected to the two current generators, drives in turn an RC network that filters the current pulses. More precisely, the RC network accomplishes two functions:

  1. to smooth down the sharp corners of the current pulses, eliminating the high frequency components around fp, 3fp, etc... This low-pass does not eliminates baseband signal frequencies that carry useful phase information from the comparator (in the figure above, this function is performed essentially by C).
  2. to filter the control loop signals so that the dynamic performances of the loop (jitter transfer, jitter tolerance, noise generation) are modified and improved. In the figure above, this second function is primarily performed by (one of) the colored RC networks.

Both filtering networks implement a 2nd order type 2 loop, the most common for charge pumps.

The network in red implements a more accurate definition of the high frequency gain of the overall loop (resistor values are more accurate than Icp values). The resistor ratio varies the loop damping factor. The resistor ratio allows also the reduction of the filter gain. An attenuation (instead of a gain) is needed to compensate for a very high gain of the VCO, which is typical of monolithic CDRs


Gain of the two main types of phase comparators[edit]

The gain of the bang-bang detector is not constant, but varies with the signal amplitude.
The gain is maximum when the difference signal at the input of the detector deviates least from its center value (from zero difference).


The gain is minimum instead when the signal deviates most from its center value.

When the gain of a bang-bang phase detector is indicated by a fixed value, that value means the minimum gain at the largest phase difference close to the output inversion.

Transfer curve and gain of the linear and of the bang-bang comparators as a function of the phase difference at their inputs



DT is a factor of the comparator gain[edit]

It is important to keep in mind that the gain curves shown for both types of phase comparator correspond to a transition density DT equal to its maximum, i.e. 100%.


When transitions are missing, which always occurs in practical cases, the DT (the average frequency of the their occurrences with respect to their possible maximum) decreases accordingly.


The gain of the comparator may decrease by the same amount as DT (unless the comparator has been deliberately made "DT independent"), and this decrease of the comparator gain affects the loop characteristics and performances.


As it will be shown , loop models with different architectures are affected differently by a gain variation Clock and Data Recovery/Conclusion#Just three models are needed for a solid background.


References[edit]

  1. a b c d Richard C. Walker (2003). "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7. http://www.omnisterra.com/walker/pdfs.papers/BBPLL.pdf. 
  2. Clock Recovery Primer, Part 2 by Guy Foster, par.10: Survey of Clock Recovery Used in Selected Standards
  3. A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit Using the Sample -and-Hold Technique by Noboru Ishihara and Yukio Akazawa, IEEE Journal of Solid-State Circuits, vol. SC-29, pp. 1566-1571, December 1994
  4. A 2.5 Gb/s Clock and Data Recovery IC with tuneable Jitter Characteristics for Use in LAN's and WAN's by Keiji Kishine, Noburu Ishihara, Ken-ichi Takiguchi, Haruhiko Ichino, 1999, a paper inserted in : Phae-Locking in High-Performance Systems, edited by Behzad Razavi 2003
  5. Hogge, C., “A Self Correcting Clock Recovery Circuit,”. IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-32, NO. 12, DECEMBER 1985, pp. 2704-2706.
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