File:Phase Detector using DETFFs and clocks I (lead) and Q (lag) at f 2.pdf
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Summary
| Description |
English: A bang-bang PD with single output and "hold" in case of lack of data transition. It is described with components typical of high-speed ICs.
The two clocks used (one is the 180° version of the other) are described as clocks coming from an oscillator at half frequency, and consequently just 90° out of phase. Both their trailing and leading transitions are used. The output is high when the main clock used for regeneration (I in the figure) lags the data, is low when the clock is early with respect to the data. |
| Date | |
| Source | Own work |
| Author | BORGATO Pierandrea |
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File history
Click on a date/time to view the file as it appeared at that time.
| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 14:05, 3 March 2014 |  | 1,754 × 1,239 (86 KB) | BORGATO Pierandrea | The output stage inversion is moved from the bottom flip-flop to the top one. The associated caption is correspondingly changed and made clearer. The waveforms in both version correspond to the schematic of this new version.~~~~ |
| 22:54, 26 February 2014 |  | 1,754 × 1,239 (84 KB) | BORGATO Pierandrea | User created page with UploadWizard |
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