Clock and Data Recovery/Structures and types of CDRs/Applications of the 2nd order type 1 architecture
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Application of the 21 architecture[edit]
This architecture is used in practice for:
 line regenerators, and for
 slave clocks in long distance (=Telecom) networks.
The implementation with linear phase comparator and linear VCO is the typical case, as it best fits the target applications.

 The linear model in this 21 case finds a direct application!
As seen in a previous page, the performance parameters to consider are ω_{n2} and ζ.
They are related to the design parameters G and τ_{f} as follows:
Setting ω_{n2} and ζ  Setting G and τ_{f} 

G = ω_{n2} / 2ζ  ω_{n2}^{2} = G/τ_{f} 
τ_{f} = 1 / 2ζω_{n2}  ζ^{2} = 1 / 4τ_{f}G 
τ_{f} is the time constant of the added filter and 1/ τ_{f} = ω_{f} its cut off frequency; G is the open loop DC gain = G_{φ} * G_{f} * G_{VCO}.
(It may also be pointed out that the 2  1 loop becomes unstable if the natural frequency ω_{n2} {that normally is about 1/2 ω_{f} or lower} gets close to ω_{f}. As ω_{n2} grows if the loop gain grows, it is not possible to use a bangbang detector because its gain varies very much with the phase difference it measures).
The ITUT Recommendations generally indicate as a reference model the 21 architecture.
For instance: “a SEC will generally mimic the behavior of a 2nd order (type 1) linear analogue phase locked loop. This allows the use of the terms (equivalent) 3 dB bandwidth and (equivalent) damping factor, as they are used in analog PLL theory, irrespective of the fact that in the implementation of a SEC, digital and/or nonlinear techniques may be used."^{[1]}
( SEC: a SDH equipment slave clock)
In fact, when requirements are the following, like in a telecom networks:
 continuous transmission mode
 receiver cost may increase if an increase of the regeneration span offers a larger saving.
These translates into:
 filtering incoming phase noise is important
 the cost of a low local noise generation is affordable
 fast acquisition is not important
then the preferred CDR implementation includes a phase comparator that behaves linearly, a low pass filter and a low noise oscillator whose frequency varies proportionally to the control signal. The PLL behaves as a 21 linear loop.
When more CDRs are chained so that their jitter transfer functions combine, then gain peaking must be minimum or absent: ζ >> 0.7.
ζ is close to 1 (0.7 to 1.3)[edit]
The value of ζ shall be set by design close to 1 (0.7 to 1.3).

 When ζ < 0.707, the jitter at frequencies around ω_{n2} will be amplified during the transit through the PLL as seen when studying the jitter transfer function of this loop, and more so for smaller values of ζ.
Amplification of jitter may  if the input jitter at those frequencies is large enough to start with  accumulate when more identical regenerators are interconnected in a chain along the signal path (a not infrequent case in geographical networks).

 When ζ >> 1, the loop behaves more and more like a first order loop. The sharp cutoff at about ω_{n2} , typical of a good 2nd order loop, smooths out, and the jitter at frequencies around ω_{n2} is less effectively rejected.
Similar indications are derived from the study of the error signal in this 21 loop.
Large values of ζ ( >> 1) involve a large error even at frequencies much lower than ; small values of ζ ( < 1.0) correspond to large overshoots of the phase error just above ω_{n2}.
Values of ζ between 0.7 and 1.3 are therefore an inevitable design choice. Other considerations that can be drawn from the study of the jitter tolerance function confirm the choice of this range of ζ values for the regenerator CDR design.
ω_{n2} and ω_{f}[edit]
The cutoff frequency of the loop filter block ω_{f} =1/τ_{f} fixes the bandwidth of the closed loop, apart from the minor adjustments of ζ as it varies within its allowed range).
The natural frequency ω_{n2} (which can also be seen as the jitter cutoff frequency of the CDR) is defined by the loop gain and by ω_{f} :
and can also be expressed as a function of just ζ and ω_{f} :
This simple formula tells that (in a 2^{nd} order PLL of type 1 where ζ_{21} must remain close to 1) the natural frequency ω_{n21} remains close to half the cutoff frequency of the loop filter!
VCO good centering and narrow jitter bandwidth
In the 2^{nd} order, type 1, loop, the VCO frequency mismatch f_{p} – f_{fr} becomes a sampling time error E_{s} according to:
(G= G_{φ}*G_{f}*G_{VCO}) For fixed open loop dc gain G and filter time constant τ_{f}, the jitter cutoff frequency ω_{n2} is:
It is easy to see that, for a 1st order type 1 loop: E_{s} = ((ω_{p} – ω_{fr}) / ω_{n1}
The same equation, rearranged, tells that the frequency mismatch and the maximum E_{s} define how tight the the loop jitter bandwidth can be:
It is easy to see that, for a 1st order type 1 loop: (ω_{n1}/ω_{p} ) = ((ω_{p} – ω_{fr}) /ω_{p}) / E_{s} )
For instance, if E_{s} is conservatively set as low as = 0.1 rad, then ω_{n2} can be : ω_{n2} ≃ 20 * (ω_{p} – ω_{fr}) .
As seen already about CDRs and parts per million of frequency mismatch, the free running frequency of a slave CDR may differ no more than 50 ppm from the frequency of its remote master (very low cost quartz crystal), or 10000 ppm (monolythic RC oscillator after EWS trimming), or even differ less than 1 ppm, still without big cost concerns (quartz for GPS receivers inside mobile phones). Less than 0.1 ppm is typical of professional equipment.
The four mentioned cases set a respective minimum for the design choice of ω_{n2} at: 0.001 ω_{p} , 0.2 ω_{p} , 2 e5 ω_{p} , 2 ppm ω_{p} .
ω_{n21} and ω_{n1}[edit]
In a 1^{st} order loop, the quantity ω_{n} = G tells how fast the loop reacts. The higher ω_{n}, the faster the loop response.
For the 2nd order loop it is difficult to relate ω_{n2} to how fast the loop reacts to a change. In the 2  1 loop, for ζ ≈ 1, and setting for sake of comparison the gain G equal for the two loops:
In other words a 2^{nd} order type 1 PLL (ζ ≈ 1) wold seem twice as “fast” as a 1st order PLL of the same gain!
But it can also be seen that, setting, for sake of comparison, ω_{n2} = ω_{n}, then the 2nd order type 1 loop is not practically slower than the 1st order loop!
 “Slow or fast” in the sentences above means both:
  slow or fast to acquire the lock condition
  slow or fast to drift to its free running frequency when the input signal disappears.
Note that the USR of the 1  1 loop model is plotted for two different values of ω_{n1}: ω_{n1} = ω_{n2} of the other two loops and 1/2 ω_{n1} = ω_{n2} of the other two loops
External References[edit]
 ↑ ITUT G.813 (03/2003) Timing characteristics of SDH equipment slave clocks (SEC), Appendix II: Considerations on bandwidth requirements, noise accumulation and payload wander accumulation, II.1 Introduction.