Clock and Data Recovery/Introduction/Acquisition, tracking and jitter performances

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Requirements and characteristics[edit]

What are the different requirements for the extraction of the clock from an incoming (encoded) bit stream?

They are essentially related to two different conditions of the CDR operation:

  1. Acquisition of the phase lock
  2. Tracking of the acquired phase timing once the acquisition is sufficient.


Acquisition[edit]

This condition of the CDR operation starts when :

  • the CDR has been turned ON, and
  • the input signal appears.
As long as the received signal is not present, the CDR is kept idle by the LOS control signal, which is generated by the first stages of the receiver, (LOS = Loss Of Signal).
When the LOS is deactivated, the CDR is released and the acquisition phase begins.
The local oscillator of the CDR at that moment has an unpredictable phase mismatch with the phase of the incoming signal.
The CDR then reacts as if it had been in perfect lock and the phase of the input signal had taken an abrupt step change.
It may be added that, in case the CDR operates as a slave CDR, it would also be subject to the equivalent to an abrupt, though small, change of the frequency of the input signal.
In fact, the input signal (during LOS) was unknown and the CDR acted as if the input signal frequency was its own free-running frequency, ffr..

The acquisition ends when the tracking begins.

The condition of tracking starts when the CDR keeps consistently its sampling point close enough to the eye center.

Close enough means that the sampling time (affected by jitter and possibly by a systematic steady state error) remains close enough to the optimum sampling point to achieve a very low Bit Error Rate.
For example, remaining within a sampling error of ±0.5 rad ( = ±0,07 U.I.) and below a BER of 10-12 could be considered as being in the tracking stage of the CDR operation.

An abrupt step of the phase of the input signal can be studied as a new acquisition with the same initial phase mismatch.


Different CDR architectures behave differently, also during the acquisition phase.

Acquisition bears a strong analogy with the unit step response of a linear systems.

In fact, if a CDR can be adequately modelled by a linear system, its acquisition is modelled by the (Unit) Step Response of the system.
Responses of the 3 fundamental linear models of PLL to an input step of 1 rad.
Parameters are chosen to have a meaningful comparison, although the value of ζ for the second order loops is lower than the values used in practice.
In other words, the two 2nd order loops are under-damped to stress the differences amongst different architectures.


Many non-linear factors may strongly influence how the acquisition evolves into tracking. For instance, the use of a bang-bang phase detector, the slew-rate consequence of the limited swing range of the VCO, the use of a PFD, each gives the acquisition transient special characteristics.

  • a linear phase comparator and input conditions that allow the other blocks to remain within their linearity ranges, make the VCO phase follow a typical catch-up with the input phase that is exponential and make the time to reach tracking independent from the amplitude of the input step (the response time τ is dependent only on the circuit characteristics and remains the same if the phase step to catch up is bigger or smaller) - See the figure above;
  • a bang-bang phase detector makes the acquisition follow a constant slope until catch-up has taken place. The slope is the same for different step amplitudes.
  • a PFD makes the CDR output phase (as long as slips of decreasing frequency precede the achievement of tracking) follow a sort of parabolic shape (spanning as many 2π multiples as the number of slips that took place) before completing the acquisition.


The simplest architecture (1st order and type 1) is best fit to implement CDRs with fast and slip-free acquisition of phase lock.

Its response to an abrupt change of phase (step input), even if combined with a frequency difference between the timing of the received signal and the free running frequence of the local oscillator (ramp input), is always free from slips .
The phase difference during the acquisition is always a decreasing function (apart from a small drift that may originate by ffr / fp mistuning and that would only be evident during periods of missing transitions and only if the mistuning sign was making the VCO resist the direction of the acquisition transient).
The simulation uses 3000 discrete time steps. Each time increment  is 2,7 ps (that is the line pulse period of 100 ps divided by 37).After 200 time steps (i.e. after .2,7 * 37 = 543  ps) the loop - that was until then open (because LOS was = 1)  starts its acquisition phase ( LOS = 0). The input phase takes  in that moment a positive step of  1.3 rad.The input transitions appear with an average density of 50 %, but otherwise in a fully random sequence..The acquisition lasts for a little over 3 ns in this example. It ends when the phase error settles around its final value (settles around 0 rad in this example).The pattern of pulses in the signal that drives the VCO (black trace) is, although random, constantly made only of positive pulses during the acquisition of lock.It may be noted that the VCO has a ffr lower than fp (in actuality lower by  5750 ppm), as the VCO phase lags behind the input phase (lower negative slope in the red trace) every time  the VCO drive signal it at its intermediate level, both before detection of the input signal and when there is a lack of transition (mid level of the VCO drive signal).The steeper slopes of the red trace, positive and negative, tell when the VCO is driven to its top and bottom frequencies (1,00575 1010 ±2,39 108 Hz ) by the positive and negative pulses of its drive signal.The drive signal is exponentially smoothed when it goes down to zero, because there is a parasitic low-pass (at 6,28 1011 rad/sec = ten time ti line pulse frequency) just after the ternary phase detector. It is sharp at its top and  bottom corners because the it is clamped by an instantaneous circuit. The acquisition time would vary every time with the randomness of the transitions at the signal appearance, and  be significantly longer than in the example with a non-zero probability.If the transitions density had been equal to 100%, the acquisition would have been faster and  predictable.
Acquisition and tracking with signal transitions occurring at random, but with an average density (i.e. DT) of 50%
In the figure above, the simulation uses 3000 discrete time steps. Each time increment is 2,7 ps (that is the line pulse period of 100 ps divided by 37).
After 200 time steps (i.e. after .2,7 * 37 = 543 ps) the loop - that was open until then (because LOS was = 1) starts its acquisition phase ( LOS = 0).
The input phase takes in that moment a positive step of 1.3 rad.
The input transitions appear with an average density of 50 %, but otherwise in a fully random sequence.
The acquisition lasts for a little over 3 ns in this example. It ends when the phase error settles around its final value (settles around 0 rad in this example).
The pattern of pulses in the signal that drives the VCO (black trace) is, although random, constantly made only of positive pulses during the acquisition of lock.
It may be noted that the VCO has a ffr lower than fp (in this example lower by exactly 5750 ppm), as the VCO phase lags behind the input phase (lower negative slope in the red trace) every time the VCO drive signal it at its intermediate level, both before detection of the input signal and when there is a lack of transition (mid level of the VCO drive signal).
The steeper slopes of the red trace, positive and negative, tell when the VCO is driven to its top and bottom frequencies (1,00575 1010 ±2,39 108 Hz ) by the positive and negative pulses of its drive signal.
The drive signal is exponentially smoothed when it goes down to zero, because there is a parasitic low-pass (at 6,28 1011 rad/sec = ten time ti line pulse frequency) just after the ternary phase detector. It is sharp at its top and bottom corners because the it is clamped by an instantaneous circuit.
The acquisition time would vary every time with the randomness of the transitions at the signal appearance, and be significantly longer than in the example with a non-zero probability.
If the transitions density had been equal to 100%, the acquisition would have been faster and predictable.
The following figure gives an example of the same circuit if the transition density is forced to 100%.
Acquisition with a preamble of 101010.. of adequate duration, are a standard in systems that frequently need to reacquire the signal lock.
When DT = 100%, it is even more evident that the tracking of a fp higher than ffr is the cause of a ratio of positive pulses to negative pulses (evident in the VCO drive signal) that is higher than 1.
Acquisition and tracking with signal transitions with an average density (i.e. DT) of 100%.
The bit strem as this density is fully predictable and cannot carry any information:
in real systems it may occur only during periods of acquisition or when there is no information to transfer.


There are other CDRs (based on the other two more sophisticated architectures, the "second order loops of type 1 and 2") whose acquisition is inevitably long and sometimes a series of slips precedes the achievement of a stable acquisition.

Slips during acquisition in a 2nd order type 1 loop with linear phase comparator.
The input frequency of the input signal is slightly lower than nominal, making the input phase exhibit a decreasing slope in addition to a sinusoidal jitter.

The presence of slips at the beginning of the acquisition is acceptable in applications operating in (Continuous transmission mode), and in inevitable in some of those, when a PFD must be used.

Tracking[edit]

Unstable acquisition with periodic slips.png
Poor tracking: when the input jitter becomes larger, the loop slips twice, then locks-in again.

All CDRs[edit]

To study the tracking state, the fundamental characteristic of all CDRs is:

  • the ability to operate correctly (that is with a low enough Bit Error Rate = BER) in the presence of a given jitter. This is called Jitter Tolerance (or Jitter Acceptance), and is often specified as a mask of jitter amplitude versus jitter frequency. The circuit must operate correctly at any condition defined by a jitter amplitude and a jitter frequency within the boundary set by the mask. In other words, the locus of the conditions of onset of BER shall be measured and found above (=at higher jitter magnitudes than) the boundary set by the mask.

Regenerator (*) CDRs[edit]

(*) A regenerator CDR is a slave CDR that is used as a master for at least another CDR further downstream.


When the CDR regenerated clock times the regenerated data stream that is resent further on (which is a common case), two other characteristics are important as well:

  • the filtering of jitter frequencies above the frequency range involved in the lock-in and tracking. This is called Jitter Transfer function, and there often exists a mask setting an upper limit for the curve that characterizes our circuit (the jitter transfer function is the ratio, at any given frequency, of the magnitude of the sinusoidal jitter at the output to the magnitude of the sinusoidal jitter at the input).
The presence of a filter block in the 2nd order PLL allows one more degree of design freedom (instead of τ only, ωn and ζ can be chosen). The 2nd order architecture is used when particular requirements (for jitter and/or noise and/or effects of non-linearities filtering) make the 1st order PLL inadequate. The quantity ωn essentially defines the cut off frequency of the low pass effect that such PLL has on the incoming jitter.


  • the amount of Generated Jitter inside our circuit (phase noise added to the retrieved timing signal). Often specified as:
    • a rms or peak value for the output wander ( < 10 Hz) with zero input wander, and
    • as a curve of maximum magnitude vs frequency for jitter (> 10 Hz).

See, for instance, the TDEV (Time Deviation) and the MTIE (Maximum Time Interval Error) used by the ITU-T inside its Recommendations [1] [2]for wander limit definition, and [3] for output jitter as well.

The ITU-T, in its Recommendations Telecommunication Standardization Sector (ITU-T), is an invaluable source of theory and practical knowledge on the subject. It primarily deals with the requirements of large, geographical, networks, and therefore these Recommendations are especially useful, and exact in their quantitative references, for the engineer that studies Telecom digital networks, but they can also provide a lot of insight if other fields of application of CDRs are being targeted.

Acquisition and tracking[edit]

Normalized frequency and time scales[edit]

The mathematical models proposed in the following pages often use normalization of the frequency and time scales. This approach focuses on the fundamental concepts: concepts that become then easier to grasp, remember and use.

De-normalization puts the actual value of the natural angular frequency ωn, that applies to the specific case under study, in the place of the value of 1 rad/sec used for modeling.
The time τ that appears in the time functions shall be readjusted in the same way, rescaling 1 sec to its actual value of 1/(ωn) sec.

The angular frequency with which the signal pulsed are received, ωp, on the other hand, does not always appear in the models.

In fact the frequency of the received pulses fp (= ωp/(2π)) is a fundamental circuit characteristic of the phase comparator and of the VCO, that are circuits which operate at fp (= ωp/(2π)).
The filter block only instead does not have to process frequencies around fp, and very often only processes frequencies at least one or two decades lower that fp.
But, as a result of closing the loop and investigating the relation between phase of the input signal and phase of the output signal in the jω domain, the whole PLL is characterized and studied only in the same range of frequencies that the filter processes!
Not infrequently the actual value of fp is neglected in some descriptions of the PLL operation and does not even appear in most of the modeling equations.
All in all, the line pulse frequency fp appears in this book less often than one may expect!

When fp cannot be neglected[edit]

  1. fp is the frequency of the discrete time representation

The study of CDRs is the study of discrete time systems, that are sampled at the frequency of the received pulses fp.
The jω representation of the system behavior is therefore meaningful up to fp, and then shall be considered to repeat itself periodically at higher frequencies, without additional information to offer.

  1. fp - ffr as the best possible tracking

The value of fp is fundamental especially in its relation with the VCO free running frequency ffr.
This relation, in association with the PLL gain, sets the design lower limit for the bandwidth of the closed loop.
The fp-ffr difference is the cause of steady state offsets in some of the PLL nodes and appears - in the most common types of PLL, those of type 1 - as a steady state offset between input and output that is in fact a steady state deviation of the sampling time at the CDR input, away from the optimum instant. In those PLLs, as it decreases the noise immunity, it is kept to a minimum by design.

  1. Lack of regularity of the incoming pulse stream

There are also, in addition to the above considerations, a few moments during the CDR operation when the relation between fp and the loop bandwidth fn (i.e. ωn/(2π)) is important for the performances and even for the theory of operation.
It is not a big surprise that such moments are those when the received pulses lack in regularity or continuity!
Three are these important moments when fp has necessarily to be kept into account:There

  1. Start of reception. The receiver starts when a signal with sufficient power is detected by the LOS (Loss Of Signal) block, more precisely at the moment when the LOS is de-asserted.
    1. Burst mode. If the transmission system is meant to operate with intervals of no signal power alternated with intervals of normal transmission (Burst Mode System), then the CDR is based on a 1st order control loop. This type of implementation is best fit for efficient acquisition, but is not remarkable in presence of micro-interruptions or of long sequences of pulses without level transitions.
    2. Continuous mode. If instead the start of reception is a exceptional occurrence in our system (Continuous Mode System), then the CDR is based on a 2nd order control loop. This implementation suffers from longer acquisition phases, but is more resilient to micro-interruptions and to long sequences of pulses without level transitions.
  2. Micro interruptions. These are short periods during which the transmitted signal does not reach the receiver (for many, different and often queer reasons!). When such interruptions last sufficiently, the CDR may drift out of lock. When the signal re-appears, a new acquisition must start. The micro-interruption will be prolonged by the new acquisition phase. It is also possible that the CDR has slipped one or more clock cycles during the interruption: this has heavy consequences downstream where a new frame sync shall be achieved because of the slip(s): the micro interruption duration is multiplied in its propagation downstream! The risk of propagating and widening the interruptions downstream is sometimes mitigated by circuits inside the CDR that take advantage of the fast detection of the micro interruption by the LOS circuitry.
    The LOS unlocks the CDR.png
    This type of circuit forces the phase lock loop open during the LOS assertion, and lets the VCO to continue free-running without phase discontinuity, until the signal re appears. At that moment the VCO may have drifted very little and the CDR can restart sampling with a good enough phase.
  3. Lack of level transitions in the received signal (for a considerable number of pulses). This aspect is fundamental when the bits to be transmitted are sent as a pulse (bit 1) or as a no pulse (bit 0) [Return to Zero NRZ].>
    1. Line codes When the information bits are transformed into signal pulses according to a “line” code, sometimes even with more than just two signal levels, it is less probable (with some codes it is outright impossible) than a long sequence of bit 1, or of bit 0, or another special sequence of bits, results into a signal without change of level (=without signal “transitions”).
    2. Scrambler Sometimes the flow of bits to be transmitted is altered (=scrambled), before being converted into signal pulses. The scramber circuit converts any long sequence of identical bits into a sequence with frequent changes of polarity, but also renders the probability of a long sequence of identical bits inside the scrambled flow practically negligible.
    3. In the OSI stack other processes elaborate the flow of bits to be transmitted. They are located at higher levels of the OSI (Open System Interconnection model) stack; first the process corresponding to lowest OSI levels adds bits to the information bit flow, and then each of the others increasing levels in the stack follows. In ascending order:
  • level 1: S/N improvement by FEC, scrambling, TDM framing,..
  • level 2: Ethernet 8B/10B byte encoding, Ethernet frame and interframe bytes, CRC,..
  • Level 3: Internet Protocol framing,..
  • level 4: Transfer Control Protocol framing,..



In spite of all that, CDRs are frequently specified, designed and characterized in order to stay in phase lock even in presence of long sequences of identical signal pulses in the received signal (in the order of thousands of pulses and sometimes even more).

The phase error may increase to some extent, but a good lock will be recovered as soon as transitions reappear. In the meantime the recovery (=decoding) of the received pulses should take place correctly.

What happens when the received signal does not exhibit, from a certain instant on, any more transition?

The phase comparator circuit does not produce any significant output, and the PLL operates in “open loop” condition.

In all slave CDRs the sampling moment drifts away from the optimal position that corresponds to the locked condition of the PLL.
The sampling instant leaves the center of the received pulses, as the lock control is interrupted and no longer keeps input phase and local oscillation phase together.

After a while, errors may begin to appear in the data flow that comes out of the CDR, and even slips finally appear (slip = a lost or an added clock cycle with respect to the transmit clock).

It may seem that sampling samples of the same polarity should not lead to errors, even if the sampling instant drifts as described above.
This is not true in many cases: consider for instance the common case of NRZ transmission where low frequencies and d.c. have been removed from the received signal. The sequence of received pulses with the same polarity becomes something like a decaying exponential waveform that eventually disappears under the noise floor.
Either an alarm circuit intervenes to declare a LOS, or the CDR jitters randomly and outputs random bits!
The slips that inevitably take place in that condition are by themselves a problem. If a section of the network downstream is slaved to this CDR, errors will result wherever (upstream for instance) the original clock domain is re-entered.

As long as the sequence of identical pulses persists the situation worsen until the frequency of slips corresponds to the difference:

frequency of received pulses – frequency of the free running sampling frequency.

In some extreme cases, where the above difference is small, some transmission may still be possible, but with a heavy penalty in terms of error-ed bits and slips (= frequent retransmission of the blocks that are detected in error).

References[edit]

  1. ITU-T Recommendation G.810 (08/96) Definitions and terminology for synchronization networks, 4.5.17 time deviation (TDEV or sx)
  2. ITU-T Recommendation G.810 (08/96) Definitions and terminology for synchronization networks , 4.5.15 maximum time interval error (MTIE)
  3. . ITU - T G.823 The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy, 5 Network limits for traffic interfaces, and 6 Network limits for synchronization interfaces