VHDL for FPGA Design
Appearance
Software Prerequisite:
For exercises you need ISE WebPACK, a fully featured front-to-back FPGA design solution for Linux, Windows XP, and Windows 7, downloadable at no charge from Xilinx (download link). |
Contents
Combinational Logic
Sequential Logic
- D Flip Flop
- T Flip Flop
- JK Flip Flop
- 4-Bit Binary Counter with Parallel Load
- 4-Bit BCD Counter with Clock Enable
- 4-Bit Shift Register
- 4-Bit Johnson Counter with Reset
State-Machine
- State-Machine Design Example Asynchronous Counter
- State-Machine Design Example Serial Parity Generator
Design Exercises
- Example Application Serial Adder
- Example Application Using PicoBlaze
- Complete synthesisable VHDL code for Signed 32 bit Radix-16 multiplier