VHDL for FPGA Design/Priority Encoder

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Priority Encoder[edit]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity Priority_Encoder_VHDL is
   port ( Sel : in std_logic_vector(3 downto 0);
 	  encoded_data : out std_logic_vector(1 downto 0);
 	             D : out std_logic);
end entity Priority_Encoder_VHDL;
 
architecture Behavioral of Priority_Encoder_VHDL is
begin
   encoded_data <= "11" when Sel(3)='1' else
 	           "10" when Sel(2)='1' else
 		   "01" when Sel(1)='1' else
 		   "00";
   D <= '0' when Sel="0000" else '1';
end architecture Behavioral;

Simulation Waveform[edit]

 Priority enc final.png

Generated Logic Circuit[edit]

 Generated Schematic.jpg