Clock and Data Recovery/Structures and types of CDRs/Applications of the 1st order type 1 architecture

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Where used and how made[edit]

This architecture is preferred when the acquisition performances are the prime requirement, but also for applications in continuous mode (e.g. phase aligners that align signals coming into a switching matrix).

Due to its inherent simplicity and resulting robustness, it is the preferred choice in general, except when special requirements recommend 2-1 or 2-2.

In practice this means:

  • burst mode receivers
  • phase aligners
  • general purpose end points.


Although the linear model has been described in detail in the previous sections, this architecture is mostly implemented with circuits that have hard non-linearities, like bang-bang detectors.

The linear model has helped fix the concepts, but recourse to simulation - that takes into account the non-linearities- becomes necessary to investigate the CDR operation when non-linearities come into play.

For the application categories listed above, just the jitter tolerance matters, and this performance is not really affected by the use of the bang-bang approach.

The bang-bang type of phase detector is used in preference to the linear one, and -in almost all cases- the VCO is implemented with digital circuitry processing a fixed frequency signal.

The acquisition speed (that is key in burst mode) is even improved a bit by this choice.

The VCO (in case of a slave application) or the "integrator + delay-line" (in case of a phase-aligner) is driven directly by a bang-bang phase detector.
Even if the VCO was a linear one, it would operate in a bang-bang mode,
because it would jump between the two frequencies that correspond to the two levels of the detector output.
There is no risk of instability nor of deterioration of the performances of interest (acquisition time and jitter tolerance) when those non-linear blocks are used in this simple, straightforward architecture.


The phase adjustment (during the acquisition) that takes place in one clock cycle is much larger than the phase drift that results from the frequency difference between the remote transmitter and the local clock (in the case of the phase aligner, such frequency difference -i.e. phase drift- is zero by definition).
In the linear model, the response time τ is the only quantity that characterizes this type of loop.
The quantity τ is measurable as a time equal to k periods of received pulses, and can be made as short as the duration of a few -say k- received bit pulses: τ = kT.
The acquisition is achieved in a time close to τ, shorter if the initial phase mismatch is small, between equal and two or three times larger if the mismatch is maximum and depending on the phase comparator type.
There are practical cases where a linear phase comparator is used in a high speed phase aligner for burst model[1], although it is the bang-bang phase detector that best fits this architecture for the applications listed.
In a bang-bang (non-linear) implementation, that is the most common, the fundamental loop parameter is the phase adjustment during one line pulse cycle. That adjustment Δφ (expressed in radian) is:
Δφ = 2π(fmax - fp)/fp or
Δφ = 2π(fp-fmin)/fp.
These two values of phase adjustment are in practice equal or not largely different ( fmax and fmin are the two frequencies that the VCO oscillates at, when driven by the high or by the low output level of the phase detector).
The quantity Δφ, that varies inversely to the acquisition time, can correspondingly be made as large as T/k.
In a bang-bang implementation the acquisition lasts for a number of received pulsed equal to the initial phase distance, divided by Δφ.

VCO centering[edit]

Once this loop (1-1 bang-bang) has achieved lock, its sampling instant will jump back and forth around the eye center, as identified by the transitions of the incoming signal.

The jumps are either right or left by a time equal to Δφ/ωp, in a random sequence. Often a few (but not many) are in the same direction before one or more jumps in the other direction take the sampling instant back towards its best position.

The jump that comes with every signal transition also has to compensate statistically for the frequency offset between ωp and ωfr.

The jump should be small to reduce the imprecision in sampling, but it should also be large to quickly acquire lock and to compensate for the VCO frequency offset.


(The VCO frequency offset may be large if the accuracy of the VCO centering is poor ).

As seen already about CDRs and parts per million of frequency mismatch, the free running frequency of a slave CDR may differ no more than 50 ppm from the frequency of its remote master (very low cost quartz crystal), or 10000 ppm (monolithic RC oscillator after EWS trimming), or even differ less than 1 ppm, still without big cost concerns (quartz for GPS receivers inside mobile phones). Less than 0.1 ppm is typical of professional equipment.

In some cases though, the clock recovery should take place with a VCO that can vary its frequency in a range not much smaller than +/- one octave. The use of a phase-frequency detector would then be necessary.


For example, a VCO where ωfr may be 10% less than ωp would need a Δφ > 2π/10.

In the linear 1st order, type 1, loop, the VCO frequency mismatch fp – ffr becomes a sampling time error Es according to: Es = (ωp – ωfr)/G , (G= Gφ*GVCO).

For fixed open loop dc gain G , the jitter cut-off frequency ωn1 is exactly ωn1 = G.


But the bang-bang phase detector, when operating with small deviations around the eye center, has a very high equivalent gain.


For instance, if Es is conservatively set as low as = 0.1 rad, then ωn1 can be :

ωn1 ≃ 20 * (ωp – ωfr) .

Example 1[edit]

The low-pass that is always present at the output of the phase-detector must be at a frequency significantly higher than the highest frequency of the incoming jitter, or else its time constant becomes significant for the loop operation, and the model or the simulation more appropriated are the ones of the 2-1 loop (over-damped).


The following figure illustrates several features of this loop.

The values used for the quantities that influence the simulation result are indicated inside the figure.

The simulation uses 1500 discrete time steps. Each increment corresponds to 0.593 ns (that is the loop time constant of 178 ns divided by 300).

After 75 time steps (i.e. after .593 * 75 = 44.5 ns) the loop - that was until then open, LOS = 1 - starts its acquisition phase ( LOS = 0). The input jitter starts in that moment a sinusoidal variation, with an amplitude of 0.95 rad and a frequency of 10 million rad/sec.

After another 38 time steps (a total of 133 steps = a total time of 67 ns), the input jitter has a negative abrupt step of - 0.4 rad, and then a positive ramp of +0.5 rad/sec.

The incoming signal is supposed to exhibit a transition density of 50%. This is simulated simply decreasing by 0.5 the detector gain.

Time diagram obtained by simulation, with 1500 discrete instants. Many of the basic characteristics of this common CDR architecture can be pointed out.

As soon as the incoming signal is received (LOS = 0) and a phase mismatch is detected, the loop goes after it with the maximum speed.

The maximum (or minimum) speed ωmax of 6.28869e-9 rad/sec (or ωmin of 6.271321e-9 rad/sec) of the VCO correspond to the high (or to the low) output of the phase detector.

(Remark: in this example the transition density is constant and equal to 50%. This reduces the detector gain and consequently both the loop gain and the deviation fmax-fmin correspondingly. In most actual applications, the beginning of the transmission burst takes place with a sequence that assures DT = 1 for the entire expected period of acquisition).

Three points should be remarked:

  1. The phase detector (in this simulation) is followed by a low-pass filter of the first order that has a low-pass pole at ωf = 2.7 ωsimulation_samples = 4.56+009 rad/sec, that is smaller than, but close to, the line pulse frequency of 6.28+009 rad/sec. The smoothing of the rise and fall transitions of the signal that drives the VCO are nonetheless clearly visible in the figure. This point becomes very relevant for the 2-2 practical applications where it may even, in some cases, imply deterioration of the CDR performances. (the 2-1 architecture, that filters the high frequency output of the comparator by definition, is practically not exposed to the risk).
  2. The maximum slope of the sinusoidal wave of input jitter is 9.5-001*1+007 = 9.5+006 rad/sec. This exceeds the maximum tracking deviation that the VCO can offer when driven by the phase detector maximum level (deviation of +8.27+006 rad/sec )or by its minimum level (deviation of -8.69+006 rad/sec).
  3. There are relatively long periods without changes in the detector output, when the VCO is working constantly at either end of its drive range (= its maximum Δφ/Δt). This is a second condition of risk, because the loop is open in that interval of time. This requires very careful consideration in the design of the 2-2 loop that , like this one, uses the bang-bang detector and does not filter the high frequencies coming out of it.

The acquisition phase in this example is not very evident. The input starts a sinusoidal variation after 75 simulation steps, that the circuit tracks with some difficulty.
It is after 113 simulation steps (113 - 75 = 38 steps after the sinusoidal component of the input has started) that the input phase has an abrupt negative step of 0.4 rad.
At that moment the loop shows its acquisition characteristic that is to recuperate at constant Δφ/Δt, which can be seen as a constant slope in the time diagram of the example figure.
In the next example the acquisition phase is more evident.

Example 2[edit]

A phase without signal (drift free-running) followed by signal appearing with an abrupt phase jump. Later on, a sinusoidal jitter at the limit of the loop tracking is added. There is a low pass in the phase detector output at 1/10 of the pulse frequency

In this example the initial acquisition phase is evident, after the input has a negative abrupt step of phase equal to - 1.75 rad (after 175 simulation steps).

The loop to drives (almost) immediately the VCO at the lowest end of its drive range (= its minimum Δφ/Δt) and recuperates at that constant Δφ/Δt (= at a constant slope in the figure).
Like in the previous example, there is some low-pass at the charge-pump output. This is evident in the exponential rise and fall of the charge pump output when steps should ideally be present.
This low-pass is also responsible for the undershoot at the end of the acquisition phase.

The tracking phase is well shown in the following phase, that lasts until after the mid point of the time diagram.

The detector jumps back and forth very often, asking the VCO to accelerate and to decelerate, so that the output phase jumps ahead and behind the input phase correspondingly.
The high frequency pole of the charge-pump output prevents the drive level to the VCO to actually reach its range ends, but is still sufficient to have the output jump ahead and behind the input. The difference between the input frequency (500 ppm + 5 rad/sec) is small with respect to the phase jumps of the output, and is easily compensated by a small (= invisible) d.c. offset of the charge-pump output.

In the leftmost part of the figure, the input acquires an additional sinusoidal component somewhat faster than the loop ωn1.

This phase variation is slightly larger and faster than the loop can fully track: this is evident from the permanence of the phase detector output in either state for as long as it tries to track either half of the sinusoidal variation, without the typical continuous jumping back and forth that is so evident in the previous phase.

External References[edit]

  1. Dieter Verhulst, Xin Yin, Johan Bauwelinck, Peter Ossieur, Xing-Zhi Qiu and Jan Vandewege (the INTEC team of Ghent University), “A robust phase detector for 1.25Gbit/s burst mode data recovery”, IEICE Electronic Express, Vol. 1, No. 18, pp.562-567, (2004). http://www.jstage.jst.go.jp/article/elex/1/18/1_562/_article