# Clock and Data Recovery/Structures and types of CDRs/The CDR Phase and Frequency Detector PFD

## PFD Phase and Frequency Detector

Many practical (slave) clock recovery circuits with a PLL architecture require some type of frequency acquisition aid.

Exceptions are only found where very stable VCOs, such as crystal oscillators, are used to insure that the frequency error is never larger than the natural acquisition range of the PLL (that is close to the PLL closed-loop bandwidth).

Excluding these stable VCOs, and other acquisition aids, such as frequency sweeping, a frequency discriminator is required as an integral part of any phase-detector for modern monolithic CDRs ([1] pages 259..260 ).

### Frequency (comparison and) detection

A serial stream of NRZ data arriving at a pulse frequency of fp is not distinguishable form a stream at 2fp made of pairs of identical pulses, nor from a stream at 3fp made of triplets of identical pulses.

Some additional information about the absolute value of fp is necessary to correctly recover clock and data. Since the uncertainty comes in steps of 100% of fp, an indication of fp with an approximation of +/- 50% is (barely) sufficient.

In practical CDR applications the uncertainty is always contained within +/- 25% (most of this uncertainty comes from the inaccuracy of the VCO free running frequency) . Additional circuitry that can detect the frequency of the incoming data in that range will be adequate, as it will be shown.

In frequency synthesisers the problem of frequency aided acquisition is equally important as in CDRs, but in synthesisers the incoming signal and the local clock are both perfectly periodic waveforms and a phase and frequency detector with a simple architecture can be used [2]. A straight forward comparison of the respective cycle period is possible, and effective. On the other hand, synthesizers often require capture ranges well in excess of +/- 25%.
In CDRs instead, the missing transitions of the incoming signal make the frequency comparison with the local clock a more complex affair.

#### Need for frequency detection (in addition to phase detection) in CDRs

A loop filter is inserted between phase comparator and VCO, in CDRs where jitter and noise performances are important (Architectures 2 - 1 and 2 - 2).

Both for architectures 2-1 and 2-2, when high transmission speed is involved, a jitter-out / jitter-in bandwidth of about 1/1000 of the bit rate is specified by most standards [3].

The "jitter-out /Jitter-in bandwidth", called ωn2 in the modeling of these loops of the second order, is therefore specified and made by design to be around ωp/1000 ( ωp is the angular frequency of the pulses of the received stream, 2π fp = ωp).

A significant ωfr / ωp mismatch (much larger than the capture range) is often the case, in particular in large volume, cost-effective monolithic implementation, where the VCO free-running angular frequency ωfr is no more accurate than about +/- 5% ( ICs manufacturing tolerances are not tighter than ± 25 %, but recourse to trimming can correct them and reduce the inaccuracy range to something like within ± 5 % ).

The accuracy of fp is not the problem in modern networks, where it is better than +/- 50 ppm. It is the poor accuracy of the VCO free-running frequency ffr that makes the aid to the acquisition necessary. ωp = 2 π fp; ωfr = 2 π ffr
There are many more slave nodes than master nodes in a network, and the master nodes are more critical than the slaves. A larger cost (-> including a tighter accuracy) can be afforded for the masters, making ωp -that originates in a master node- (much) more accurate than ωfr -that originates in a slave receiver-.

But without aids the the capture range of the CDR is approximately coincident with +/-( jitter-in / jitter-out bandwidth) around the free-running frequency of the VCO.

If the free-running frequency is so shifted that the capture range does not include the frequency of the data to lock into, the phase comparator alone cannot make the acquisition possible.
The data transitions pass in front of the local clock faster than it can shift its frequency to catch one of them, with no chance to achieve phase lock.
In fact, these CDRs react in a time of about 1/(2 capture_range), and a new input transition shifts inside the range of the phase comparator (while the previous one "slips" away), before a significant part of the time 1/(2 capture_range) has elapsed.
The PLL goes through alternate periods of accelerating and decelerating, with slips in between, but never achieves phase lock.
Sometimes, when ωp is close to ωfr ± ωn2, a series of slips may eventually end in a good phase lock. The acquisition may be achieved but with slips and unpredictably long times.
Aided acquisition is then mandatory.

In such cases the acquisition must be aided by additional circuits that widen the capture range.

Inside a complex equipment another clock with good enough accuracy may be available. A frequency close to fp can be easily synthesized, and a frequency detector of clock differences can be used. Its output will be summed to the CDR PD output.
There have been also cases where frequency sweeping was used to have the capture range overlap fp.
Note that the VCO must be driven by a unique signal, even if the drive signal is obtained by combination of two separate ones. (A VCO with two inputs is a "bad idea" within the scope of stable control systems, see also [1] at page 261).

Tight jitter bandwidth and wide acquisition range can be achieved together if the CDR includes a Frequency Detector (FD) in addition to its Phase Detector (PD), as it is often the case[4].

Sometimes a separate FD for CDRs is used in parallel to the PD, but this is a rare occurrence.

The two blocks are normally physically and functionally combined, and the overall block/function is named phase-frequency detector PFD, which also offers the benefit of automatic transition from the operation of the one to the other as soon as lock is achieved.

A PFD may incorporate a linear PD , but more often incorporates bang-bang PD(s) [5]. The bang-bang structure of the PFD in practical applications is a consequence of the application requirements. It will be shown that the (bang-bang) PFD is used in CDRs of the 2-2 type, that are made with bang-bang detectors. Architectures of the 2-1 type normally find application in association with accurate VCOs, and architectures of the 1-1 type are used for phase aligners that have a perfectly accurate local clock by definition.

The frequency detection in practical applications is part of a monolithic implementation of the CDR, working at the highest speed that the chip technology allows. Then the implementation will be based on discrete time instants and binary signal levels, as mentioned already for PDs[6].

To reinforce the general validity of the above point, another aspect of the IC industry must be appreciated. When a new, faster chip technology appears, it will be used to create new CDRs at higher speed, as the paper emphasizes. But this new technology will NOT be used for a redesign of the CDRs made in an earlier technology pushing that technology to its speed limit. The semiconductor industry is always short of good designers, and at the same time it is difficult to replicate exactly the performances of an IC in a different, though older, technology. Additionally, customers are reluctant to undergo again the cost of chip qualification. Scarcity of design resources, risk of not making a good replica and customer reluctance for a re-qualification all cooperate to the result that a successful mixed-signal chip is practically never redesigned. This also implies that architectural alternatives of an existing solution (that become possible with the appearance of a later and faster technology) are practically never implemented!

In a CDR the Frequency Detector must accomplish a very basic, simple task: bring the VCO frequency close enough to the pulse frequency of the incoming signal, so that the Phase Detector can take effect and drive the phase lock.

Simple task entails simple requirements: the Frequency Detector need not be linear, need not offer the highest gain possible, it just shall ensure a reasonably fast frequency acquisition for realistic frequency differences and must become unnoticeable as soon as the Phase Detector is able to intervene. The important performance of the CDR are influenced by the PD, not by the FD: the FD is also required not to limit the PD performances.

The PFD of use in CDRs are of the bang-bang type. The FD function is active outside of the frequency range where the PD can capture the incoming signal, and the FD effect disappears completely as soon as the PD function can take over.

This is why the Frequency Detector is normally neglected in modeling and often also in simulation of the CDRs.

#### Methods of frequency detection

It has been shown earlier that to detect a phase difference, the transitions of the data signal are compared with the transitions of one clock.

To detect a frequency difference, the transitions of the data signal shall be compared with the transitions of two clocks of equal frequency that just have a constant phase distance. (= difference)

The comparison with one clock will produce an indication of the phase difference of the data transitions with that clock, the comparison with the second clock an indication of the difference with the second clock.

Each individual phase difference will vary with time, and indicate a constant frequency difference if it exhibits a cyclic behavior, but neither alone can tell the sign of the frequency difference!

Combining the results of the two comparisons together it is possible to identify also the sign of the frequency difference ( provided the two clocks do not differ in phase exactly by 00 nor by 1800 because the frequency difference signal would be completely attenuated in those two extreme cases! ).The best discrimination (= the strongest signal) will be obtained when their distance is chosen to be exactly 900 (or 2700).

Two clocks orthogonal with each other (that is 900 or π/2 out of phase) and each with 50% duty-cycle, make the two phase comparators divide all the 3600 of their period into 4 quadrants; the two phase comparators together indicate the quadrant where the data signal transition is located, and this info can be updated at every new data transition. This type of frequency detectors are called "rotational" frequency detectors[7]. In the same paper Donald Richman first introduced the term "quadricorrelator" applying PFD to NTSC color carrier detection in color television and describing an analog version of the circuit that uses both an In-phase and a Quadrature clock to obtain a beat note at double frequency and a d.c. component proportional to the frequency difference. (Quadrants defined with Phase and Quadrature clocks, hence the name quadricorrelator). Although the quadricorrelator operation may not be very good with the random transitions of a NRZ data stream without some modifications ([1] page 269), the I and Q technique is good also for CDR PFDs.

• I (lag), is the reference and defines with its positive transition the 0o instants. I stands for In-phase; (When PD and FD are combined and part of a CDR, then I is the clock used for data regeneration).
• Q (lead) identifies the -90o or 270oinstants. Q stands for "Quadrature".
Two synchronous clocks, 90 degrees distant from each other, divide each period T in two intervals, 1/4 T and 3/4 T.
If the two clocks have 50% duty cycle, using their negative transitions, all 4 quadrants can be identified.
I is the reference, In-phase clock, Q leads I by 90 degrees.
Before lock, the data transitions shift with respect to the two clocks.
When a data transition is first detected inside the interval "I leads Q" and then detected inside the interval "Q leads I", the data transitions are shifting to the left.
The data transitions are therefore based on a frequency lower than the frequency of the two clocks.
In such condition, the VCO of a PLL shall be driven towards a lower frequency, that is with a lower level of the VCO drive signal.
When a data transition is first detected inside the interval "Q leads I" and then inside the interval "I leads Q", the data transitions are shifting to the right.
The data transitions are then based on a frequency higher than the frequency of the two clocks.
In such condition, the VCO of a PLL shall be driven towards a higher frequency, that is with a higher level of the VCO drive signal.

If the two I and Q clocks have both 50% duty cycle, using also their negative transitions, all 4 quadrants can be identified.

The frequency sign can be obtained each time data transitions, after a detection in a given quadrant, cause a detection in a quadrant to the left (fp lags ffr), or to the right. (fp leads ffr)

#### How a bang-bang PFD is made

It is made up of two PDs and one final block that processes the outputs of the two PDs.

One PD operates on the input data stream and on the VCO clock that shall be locked to the data. This clock is called the I (= In phase) clock.

The other PD operates on the input data stream and on a VCO clock that is 90°, i.e. π/2, out of phase with the previous one. This clock is called the Q (= Quadrature) clock. It could be be +90° or -90° out of phase with I : let's choose here +90°, which means that the Q waveform lags the I waveform.

In a typical example, the two outputs from the two PDs are put together in a following block that is essentially the same as the output stage of the "hold" bang-bang PD.

The scheme of principle of a bang-bang PFD for CDRs.

This structure works with signals as follows:

• the clocks of the first PD are:
1. the clock that regenerates the data and
2. its 180° shifted version
• the clocks of the second PD are both shifted versions of the clock that regenerates the data, respectively:
1. by 90° and
2. by 270°,

The two clocks of each PD are 180° out of phase with each other.

The outputs of the two PDs are combined in a final stage identical to the final stage of the "hold" PD.

The output of the PFD may be present a polarity inversion if:

1. the shift of the Q clock of the second PD is -90° instead of +90° with respect to the clock I (the other clocks do not matter, as +180° is indistinguishable from -180°);
2. the final stage either uses an inversion after the top flip-flop or an inversion after the bottom flip-flop.

An example of the waveforms in case of a constant frequency difference is shown in the following figure (note the inversion of the PFD output):

Simulation with 3K time points of the waveforms inside a Phase and Frequency Detector of the bang-bang type. The detector is driven by one clock (input +) at 1 GHz and by another clock (input -) at 1GHz-398 ppm. After 1850 simulation samples, the input clock becomes noisy with the addition of a sinusoidal phase jitter of 0.3 rad of amplitude and of 10e+10 rad/sec of angular frequency. Note the typical pattern of the slips of the two Phase Detectors driven by I(lead) and Q(lag) that are orthogonal square waves. The wave of the Q(lag) detector seems to lead the other: this is because the frequency difference is negative. This PFD is wired so that its output is low if the negative input receives a lower frequency than the positive input, and viceversa. In many cases the output polarity is the opposite.

This system is a discrete time system with samples at frequency fVCO, and a data transition should be sampled at least once every time it drifts through one of the four quadrants. Each drift trough a quadrant should last at least 1/ (4fVCO).

A data transition has been sampled inside one quadrant. The following data transition (DT = 100%), while the data stream drifts across the quadrants defined by Q and I, should preferably be sampled (at least once) inside each quadrant. The sampling takes place if the period of 1/fVCO stays inside the range 1/fp +/- 25%.

As DT is normally lower than 100%, on each missing transition it is preferable that the PDs artificially "hold" the previous detection of the phase until a new significant detection can be made, and that the FD does the same.

##### A bang-bang PD that "holds", in a different representation

This kind of PD has already been introduced in the previous page about PDs.

It is presented again here with identical behavior, but using a different set of circuit symbols that better represent the circuit elements of a high-frequency integrated circuit.

High frequency circuits are fully differential for noise immunity, making a signal and its complement always available together. Exchanging one wire with the other of a differential pair corresponds to the inversion of the signal: no inverter stage is needed. Multiplexers are easy to implement. Two flip-flops and a multiplexer make up a double edge triggered flip-flop DETFF.

In this case, the two DETFFs allow the use of clocks at half the frequency because both edges of the clocks are used (clocks must have 50% duty cycle).

The clocks that drive the two flip-flops, are indicated as the I (lead) and Q (lag, i.e. 90° late) clock phases coming out of an oscillator that runs at half the data pulse frequency. They are equivalent to two clocks of double frequency and separated by 180°.

This anticipates the incorporation of two of these PDs in a PFD that uses their outputs to detect the sign of the frequency difference, in a CDR that uses a muli-phase VCO at half the frequency.

A bang-bang PD with output held fixed if the incoming data miss one or more transitions, rendering the PD gain independent from the transition density.

The output of the first DTEFF carries the regenerated data, the output of the second DETFF carries the cross-over samples taken at the instant when a data transition is expected.

It may be noted that this PD is made up of three DETFFs, but the third is slightly modified with an inversion at the output of its lower flip-flop.

This inversion in the last stage sends to the output the last cross-over sample when the data have a positive transition and as long as they stay high, the opposite of the last cross-over sample when the data have a negative transition.

Inverting on negative transitions and not inverting on positive ones makes the PD output go high if the clock lags the data, and viceversa.

##### A bang-bang PFD with reduced VCO frequency for easier implementation inside an IC
A bang-bang PFD that can be driven by a VCO at f/2
The inversion placed on the bottom flip-flop causes the PFD to a high output if the VCO frequency is higher than the data frequency
(the inversion should be on the top flip-flop is the PFD shall have a low output when fVCO < fp and a high output if fVCO < fp.).

When the PFD is inserted in a CDR that reaches the phase lock, its output replicates the output (or the inverted output) of the PD that acts as clock of the PFD final stage.

This is obtained by inverting the output of the top flip-flop in the final stage if the second PD uses a clock 90° in advance, and inverting the output of the bottom flip-flop in the final stage if the second PD uses a clock that is 90° late (like in the waveform and in the schematic of the figure above).

#### Acquisition of Frequency and Phase Lock

Simulation of the acquisition phase of a PLL 2nd order type 2 with a bang-bang Phase and Frequency Detector.

[1]

[1]

### External References

1. Aaron BUCHWALD and Kenneth W. MARTIN, 1995, Integrated Fiber Optic Receivers http://www.mobius-semiconductor.com/whitepapers/IntegratedFiberOpticReceivers_crop.pdf
2. http://www.unhas.ac.id/rhiza/arsip/research-stuffs/Phase-Locked/218-PhaseDetector-2.pdf
3. Clock Recovery Primer, Part 2 by Guy Foster, par.10: Survey of Clock Recovery Used in Selected Standards
4. Behzad Razavi, Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits-A Tutorial, 4.6 Aided Acquisition, downloadable at: http://itee.uq.edu.au/~coms3100/coms3100/Lecture%20Notes/Razavi1996_PLL_IEEExplore.PDF
6. Richard C. Walker (2003). "Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems". pp. 34-45, a chapter appearing in "Phase-Locking in High-Performance Sytems - From Devices to Architectures", edited by Behzad Razavi, IEEE Press, 2003, ISBN 0-471-44727-7.
7. Donald Richman. Color-carrier reference phase synchronization accuracy in NTSC color television. Proc. IRE, 42:106–133, January 1954.
8. P.E.Allen, June 26 2003, Lecture 200 - Clock and Data Recovery Circuits from ECE 6440, http://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L200-CDR-I(2UP).pdf

### Application of the 2-1 architecture

This architecture is used in practice for:

• line regenerators, and for
• slave clocks in long distance (=Telecom) networks.

The implementation with linear phase comparator and linear VCO is the typical case, as it best fits those target applications.

This architecture yield the better high frequency rejection (40 dB/dec), that is important when long distance links (=large distortions) affect the line signal with ISI and noise.

The use of a linear comparator gives very little noise generation (in contrast to a possible bang-bang alternative).

Applications inside long distance equipment are less cost sensitive, and therefore use of linear VCOs with low noise and good linearity is possible.

Linearity of the characteristics all PLL elements allows matching tight, demanding specifications that are typical of the Telecom world.

The cascading of of several CDRs in a long distance connection becomes possible because of the low noise generation, good input noise rejection and predictable characteristics.

The linear model of the 2-1 architecture is really and directly useful because of its correspondence to the actual circuit implementation!

The ITU-T Recommendations generally indicate as a reference model the 2-1 architecture.

For instance: “a SEC will generally mimic the behavior of a 2-nd order (type 1) linear analogue phase locked loop. This allows the use of the terms (equivalent) 3 dB bandwidth and (equivalent) damping factor, as they are used in analog PLL theory, irrespective of the fact that in the implementation of a SEC, digital and/or non-linear techniques may be used."[1]

( SEC: a SDH equipment slave clock)

In fact, when requirements are the following, like in a telecom networks:

• continuous transmission mode
• receiver cost may increase if an increase of the regeneration span offers a larger saving.

These translates into:

• filtering incoming phase noise is important
• the cost of circuitry with low noise generation is affordable
• fast acquisition is not important

then the preferred CDR implementation includes a phase comparator that behaves linearly, a low pass filter and a low noise oscillator whose frequency varies proportionally to the control signal. The PLL behaves very much as a 2-1 linear loop.

When more CDRs are chained so that their jitter transfer functions combine, then gain peaking must be minimum or absent: ζ >> 0.7.

#### edit section

As seen in a previous page, the performance parameters to consider are ωn2 and ζ,

as well as the design parameters G and τf , where τf is the time constant of the added filter and 1/ τf = ωf its cut off frequency; G is the open loop DC gain = Gφ * Gf * GVCO.

τf may vary within a +/- 30% range, but G may vary in a much wider range because it is linked also to the transition density.

If the filtering caracteristics ( τf ) are kept fixed, and just the open loop gain is varied:

ωn212 = G / τf and ζ212 =1 / ( 4 G τf)
the 2-1 gets less damped with more gain, i.e. more damped with less gain.
This behaviour of ζ21 with respect to the loop gain G explains why 2-1 is not used with bang-bang phase detectors nor VCOs that have a highly variable gain.
• The interesting characteristics of the 2-1 (rejection of the signal jitter, that make it preferred for regenerator applications) depends on a good control of the damping ratio, ζ21 . ζ21, in turn, depends on the loop gain G and decreases when G increases (risk of jitter peaking!): ζ212 =1 / ( 4 G τf).

It is important to keep in mind that the value of τf may vary in certain interval (e.g. +/- 30% because of manufacturing variability, ageing, power supply and temperature), but that G varies in a wider range because, in addition to the same factors that affect τf, Gφ in particular is affected by the transition density of the incoming signal.

Depending on the applications, DT maybe considered as practically constant and equal to 50% (8B10B, 64/66 with scrambling, ...), or variable in a somewhat wider range around 50%. In this second case, the loop gain G variability is correspondingly larger.

What is important is that this 2-1 loop has the lowest ζ when G is maximum, and therefore the design constraint is to use the maximum value of G to match the minimum value allowed for ζ. When transition density decreases and G decreases, then ζ increases and an overdamping of the characteristic must be accepted (the two poles of the characteristic of jitter transfer may become real and separate, degrading to some extent the valuable characteristics of this 2-1 loop. (It may also be pointed out that the 2 - 1 loop becomes unstable if the natural frequency ωn2 {that normally is about 1/2 ωf or lower} gets close to ωf. As ωn2 grows if the loop gain grows, it is not possible to use a bang-bang detector because its gain varies very much with the phase difference it measures).

#### ζ is close to 1 (0.7 to 1.3)

The value of ζ shall be set by design close to 1 (0.7 to 1.3).

Amplification of jitter may - if the input jitter at those frequencies is large enough to start with - accumulate when more identical regenerators are interconnected in a chain along the signal path (a not infrequent case in geographical networks).

• When ζ >> 1, the loop behaves more and more like a first order loop. The sharp cutoff at about ωn2 , typical of a good 2nd order loop, smooths out, and the jitter at frequencies around ωn2 is less effectively rejected.

Similar indications are derived from the study of the error signal in this 2-1 loop.

Large values of ζ ( >> 1) involve a large error even at frequencies much lower than $\omega_{n2}$; small values of ζ ( < 1.0) correspond to large overshoots of the phase error just above ωn2.

Values of ζ between 0.7 and 1.3 are therefore an inevitable design choice. Other considerations that can be drawn from the study of the jitter tolerance function confirm the choice of this range of ζ values for the regenerator CDR design.

#### ωn2 and ωf

The cut-off frequency of the loop filter block ωf =1/τf fixes the bandwidth of the closed loop, apart from the minor adjustments of ζ as it varies within its allowed range).

The natural frequency ωn2 (which can also be seen as the jitter cutoff frequency of the CDR) is defined by the loop gain and by ωf :

ωn22 = Gωf

and can also be expressed as a function of just ζ and ωf :

ωn21 = ωf /2ζ21

This simple formula tells that (in a 2nd order PLL of type 1 where ζ21 must remain close to 1) the natural frequency ωn21 remains close to half the cutoff frequency of the loop filter!

In the 2nd order, type 1, loop, the VCO frequency mismatch fp – ffr becomes a sampling time error Es according to:

Es = (ωp – ωfr)/G

(G= Gφ*Gf*GVCO) For fixed open loop dc gain G and filter time constant τf, the jitter cut-off frequency ωn2 is:

ωn2 = G * 2ζ
Es = ((ωp – ωfr) * 2ζ ) / ωn2

It is easy to see that, for a 1st order type 1 loop: Es = ((ωp – ωfr) / ωn1

The same equation, rearranged, tells that the frequency mismatch and the maximum Es define how tight the the loop jitter bandwidth can be:

Es / 2ζ = (ωp – ωfr) / ωn2 = ((ωp – ωfr)/ωp) / (ωn2p)
n2 / ωp ) = ((ωp – ωfr) /ωp) / (Es /2ζ ))

It is easy to see that, for a 1st order type 1 loop: (ωn1p ) = ((ωp – ωfr) /ωp) / Es )

For instance, if Es is conservatively set as low as = 0.1 rad, then ωn2 can be : ωn2 ≃ 20 * (ωp – ωfr) .

As seen already about CDRs and parts per million of frequency mismatch, the free running frequency of a slave CDR may differ no more than 50 ppm from the frequency of its remote master (very low cost quartz crystal), or 10000 ppm (monolythic RC oscillator after EWS trimming), or even differ less than 1 ppm, still without big cost concerns (quartz for GPS receivers inside mobile phones). Less than 0.1 ppm is typical of professional equipment.

The four mentioned cases would set a respective minimum for the design choice of ωn2 at: 0.001 ωp , 0.2 ωp , 2 e-5 ωp , 2 ppm ωp .

For a 2-1 loop when high transmission speed is involved, a jitter-out/jitter-in bandwidth of about 1/1000 of the bit rate is specified by most standards Clock Recovery Primer, Part 2 by Guy Foster, par.10: Survey of Clock Recovery Used in Selected Standards. Therefore the typical limit for ωn2 to respect is .....

#### ωn21 and ωn1

In a 1st order loop, the quantity ωn = G tells how fast the loop reacts. The higher ωn, the faster the loop response.

For the 2nd order loop it is difficult to relate ωn2 to how fast the loop reacts to a change. In the 2 - 1 loop, for ζ ≈ 1, and setting -for sake of comparison- the gain G equal for the two loops:

ωn21 = 2ζ21 G
ωn21 ≈ 2 ωn1

In other words a 2nd order type 1 PLL (ζ ≈ 1) wold seem twice as “fast” as a 1st order PLL of the same gain!

But it can also be seen that, setting, for sake of comparison, ωn2 = ωn, then the 2nd order type 1 loop is not practically slower than the 1st order loop!

“Slow or fast” in the sentences above means both:
- slow or fast to acquire the lock condition
- slow or fast to drift to its free running frequency when the input signal disappears.
The following figure contrasts the Unit Step Responses of the 3 important PLL models:
USRs of the 3 important loop models.
2 - 1 and 2 - 2 are plotted for natural undamped frequency = 6.28 Grad/sec and ζ = 1
1 -1 is plotted for both natural frequency = 6.28 Grad/sec and 3.14 Grad/sec.

Note that the USR of the 1 - 1 loop model is plotted for two different values of ωn1: ωn1 = ωn2 of the other two loops and 1/2 ωn1 = ωn2 of the other two loops

### References

1. ITU-T G.813 (03/2003) Timing characteristics of SDH equipment slave clocks (SEC), Appendix II: Considerations on bandwidth requirements, noise accumulation and payload wander accumulation, II.1 Introduction.
2. 1MA98: dB or not dB? Rohde & Schwarz Application Note http://www2.rohde-schwarz.com/file_5613/1MA98_4E.pdf
3. Telecommunications: Glossary of Telecommunication Terms Federal Standard 1037C August 7, 1996 http://www.its.bldrdoc.gov/fs-1037/fs-1037c.htm

div class="noprint" alone