User:BORGATO Pierandrea

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Application of the 2-1 architecture[edit]



This architecture uses the option of a single pole (lowpass) filter in the stage between phase comparator and VCO.

The low-pass (-20 dB/dec) of the frequencies above ωf in the filter stage between comparator and VCO becomes - 40 dB/dec in closed loop performance (for frequencies higher than ωn2 = √G/τf).

The maximum output of the comparator, multiplied by the finite d.c. gain of the filter stage, corresponds to the maximum frequency deviation of the VCO, but it can only be reached with a delay proportional to 1 / ωf.

It's like driving using either the accelerator or the brake, with a certain delay both to switch between them and to increase pressure on either pedal.

It is easy to understand that this architecture does not react to fast spurious signals, and that it rejects the high frequencies of the input jitter.

Inevitably, it is sub-optimal during acquisition (for which the 1 - 1 provides better performances), suffers from finite steady-state error (such error is zero with a 2-2 architecture) and is only useful when the regenerated clock must be re-used for further transmission, i.e. when the regenerated clock must be cleaned from received jitter and locally generated VCO noise. (regenerators only).

The implementation with linear phase comparator and linear VCO is the typical case, as it is necessary to reduce noise and to de-jitterize with controlled bandwidth.

The use of linear circuit blocks in these applications makes the linear model of the 2-1 architecture really and directly useful!

Where used and how made[edit]

This architecture is used in practice for:

  • line regenerators in general,
  • slave clocks in long distance (=Telecom) networks,
  • Second stage PLLs in line regenerator equipment (de-jitterisers).

This architecture ( of the two 2nd order architectures type 1 or type 2) was used first because it can be implemented with simpler circuitry:

  • the filter can be a passive circuit without amplification;
  • the VCO can be obtained from a quartz oscillator just making the parallel capacitance variable.

It was in fact the only second order architecture considered in the early technical literature on PLLs (e.g. [1].

As more complex circuitry became available at ever decreasing costs, it got replaced in many cases by the more versatile 2-2 one, except where its peculiar characteristics are really useful. In some cases (line regenerators) there are now one of each in every equipment, to take advantage of the strong points of both.

This is the architecture that produces the sharpest high frequency rejection (40 dB/dec) of input high-frequency jitter and of low-frequency internal noise, that is important when a clean clock must be extracted from the input signal.

  • long distance links (=large distortions) affect the line signal with ISI and noise;
  • regenerators are connected in series to cover a very long distance span, so that the jitter/noise in the pass band might be repeatedly amplified.

The use of a linear comparator (in contrast to a possible bang-bang alternative) generates very little noise.

The use of a linear comparator and of a linear VCOs with low noise and good linearity may lead to very good regenerator performances, but is associated with somewhat higher costs and limitations of the highest fp of operation.

The tight accuracy that must be met by the ffr of the VCO may be incompatible with a monolithic implementation, unless a PFD is used (contrast jitter BW and VCO noise spectrum...).

This is a type 1 architecture and therefore its sampling error ... and closed loop bandwidth ... depend on the VCO ffr accuracy

If cost targets can must be met with a monolithic implementation, then As applications inside long distance equipment are less cost sensitive,

The application of all PLL elements within their linear range allows to match the tight, demanding specifications that are typical of the Telecom world.

The cascading of of several CDRs in a long distance connection becomes possible because of the low noise generation, good input noise rejection and predictable characteristics[2].

Amplification of any jitter frequency should be minimal ( P, the maximum gain peaking, must be less than 0,1 dB in chain of repeaters [3], and of 0.3 dB at most in other standards [4].

The ITU-T Recommendations generally indicate as a reference model the model that corresponds to the 2-1 architecture.

For instance:
“a SEC will generally mimic the behavior of a 2-nd order (type 1) linear analogue phase locked loop. This allows the use of the terms (equivalent) 3 dB bandwidth and (equivalent) damping factor, as they are used in analog PLL theory, irrespective of the fact that in the implementation of a SEC, digital and/or non-linear techniques may be used."[5]
( SEC: a SDH equipment slave clock)

In fact, when requirements are the following, like in a telecom networks:

  • continuous transmission mode
  • receiver cost may increase if an increase of the regeneration span offers a larger saving.

They translates into:

  • filtering incoming phase noise is important
  • the cost of circuitry with low noise generation is affordable
  • fast acquisition is not important

then the preferred CDR implementation includes a phase comparator that behaves linearly, a low pass filter and a low noise oscillator whose frequency varies proportionally to the control signal. The PLL behaves very much as a 2-1 linear loop.

When more CDRs are chained so that their jitter transfer functions combine, then gain peaking must be minimum or absent: ζ >> 0.7.

Loop parameters[edit]

As seen in the previous page, the loop model is defined either by its performance parameters ωn2 and ζ , or by its design parameters G and τf,

2nd order PLL of type 1: relations between performance and design parameters
 Setting ωn2 and ζ   Setting G and τf 
G = ωn2 / 2ζ ωn22 = G/τf
τf = 1 / 2ζωn2 ζ2 = 1 / 4τfG

τf may vary within a +/- 30% range, but G may vary in a much wider range because it is linked also to the transition density.

If the filtering caracteristics ( τf ) are kept fixed, and just the open loop gain is varied:

ωn212 = G / τf and ζ212 =1 / ( 4 G τf)
the 2-1 gets less damped with more gain, i.e. more damped with less gain.
This behaviour of ζ21 with respect to the loop gain G explains why 2-1 is not used with bang-bang phase detectors nor VCOs that have a highly variable gain.
  • The interesting characteristics of the 2-1 (rejection of the signal jitter, that make it preferred for regenerator applications) depends on a good control of the damping ratio, ζ21 . ζ21, in turn, depends on the loop gain G and decreases when G increases (risk of jitter peaking!): ζ212 =1 / ( 4 G τf).

It is important to keep in mind that the value of τf may vary in certain interval (e.g. +/- 30% because of manufacturing variability, ageing, power supply and temperature), but that G varies in a wider range because, in addition to the same factors that affect τf, Gφ in particular is affected by the transition density of the incoming signal.

Depending on the applications, DT maybe considered as practically constant and equal to 50% (8B10B, 64/66 with scrambling, ...), or variable in a somewhat wider range around 50%.

In this second case, the loop gain G variability is correspondingly larger.

What is important is that this 2-1 loop has the lowest ζ when G is maximum, and therefore the design constraint is to use the maximum value of G to match the minimum value allowed for ζ. When transition density decreases and G decreases, then ζ increases and an overdamping of the characteristic must be accepted (the two poles of the characteristic of jitter transfer may become real and separate, degrading to some extent the valuable characteristics of this 2-1 loop. (It may also be pointed out that the 2 - 1 loop becomes unstable if the natural frequency ωn2 {that normally is about 1/2 ωf or lower} gets close to ωf. As ωn2 grows if the loop gain grows, it is not possible to use a bang-bang detector because its gain varies very much with the phase difference it measures).

edit section[edit]

ζ close to 1 (0.7 to 1.3) at minimum DT[edit]

The value of ζ shall be set by design close to 1 when DT is at its minimum expected value.

In other words ζ during real operation (taking into account all factors, including manufacturing variations of each different unit) may be found anywhere in the range 0.7 to 3 or 4.

Amplification of jitter may - if the input jitter at those frequencies is large enough to start with - accumulate when more identical regenerators are interconnected in a chain along the signal path (a not infrequent case in geographical networks) and eventually deteriorate the jitter tolerance beyond the acceptable boundary.
  • When ζ >> 1, the loop behaves more and more like a first order loop. The sharp cutoff at about ωn2 , typical of a good 2nd order loop, smooths out, and the jitter at frequencies around ωn2 are less effectively rejected.

Similar indications are derived from the study of the error signal in this 2-1 loop.

Large values of ζ ( >> 1) involve an appreciable error even at frequencies much lower than \omega_{n2};
small values of ζ ( < 1.0) correspond to large overshoots of the phase error just above ωn2.

Values of ζ between 0.7 and 1.3 are therefore an inevitable design choice. Other considerations that can be drawn from the study of the jitter tolerance function confirm the choice of this range of ζ values for the regenerator CDR design.

ωn2 and ωf[edit]

The cut-off frequency of the loop filter block ωf =1/τf fixes the bandwidth of the closed loop, apart from the minor adjustments of ζ as it varies within its allowed range).

The natural frequency ωn2 (which can also be seen as the jitter cutoff frequency of the CDR) is defined by the loop gain and by ωf :

ωn22 = Gωf

and can also be expressed as a function of just ζ and ωf :

ωn21 = ωf /2ζ21

This simple formula tells that (in a 2nd order PLL of type 1 where ζ21 must remain close to 1) the natural frequency ωn21 remains close to half the cutoff frequency of the loop filter!

VCO good centering and narrow jitter bandwidth

In the 2nd order, type 1, loop, the VCO frequency mismatch fp – ffr becomes a sampling time error Es according to:

Es = (ωp – ωfr)/G

(G= Gφ*Gf*GVCO) For fixed open loop dc gain G and filter time constant τf, the jitter cut-off frequency ωn2 is:

ωn2 = G * 2ζ
Es = ((ωp – ωfr) * 2ζ ) / ωn2

It is easy to see that, for a 1st order type 1 loop: Es = ((ωp – ωfr) / ωn1

The same equation, rearranged, tells that the frequency mismatch and the maximum Es define how tight the the loop jitter bandwidth can be:

Es / 2ζ = (ωp – ωfr) / ωn2 = ((ωp – ωfr)/ωp) / (ωn2p)
n2 / ωp ) = ((ωp – ωfr) /ωp) / (Es /2ζ ))

It is easy to see that, for a 1st order type 1 loop: (ωn1p ) = ((ωp – ωfr) /ωp) / Es )

For instance, if Es is conservatively set as low as = 0.1 rad, then ωn2 can be : ωn2 ≃ 20 * (ωp – ωfr) .

As seen already about CDRs and parts per million of frequency mismatch, the free running frequency of a slave CDR may differ no more than 50 ppm from the frequency of its remote master (very low cost quartz crystal), or 10000 ppm (monolythic RC oscillator after EWS trimming), or even differ less than 1 ppm, still without big cost concerns (quartz for GPS receivers inside mobile phones). Less than 0.1 ppm is typical of professional equipment.

The four mentioned cases would set a respective minimum for the design choice of ωn2 at: 0.001 ωp , 0.2 ωp , 2 e-5 ωp , 2 ppm ωp .

For a 2-1 loop when high transmission speed is involved, a jitter-out/jitter-in bandwidth of about 1/1000 of the bit rate is specified by most standards [6]. Therefore the typical limit for ωn2 to respect is .....

ωn21 and ωn1[edit]

In a 1st order loop, the quantity ωn = G tells how fast the loop reacts. The higher ωn, the faster the loop response.

For the 2nd order loop it is difficult to relate ωn2 to how fast the loop reacts to a change. In the 2 - 1 loop, for ζ ≈ 1, and setting -for sake of comparison- the gain G equal for the two loops:

ωn21 = 2ζ21 G
ωn21 ≈ 2 ωn1

In other words a 2nd order type 1 PLL (ζ ≈ 1) wold seem twice as “fast” as a 1st order PLL of the same gain!

But it can also be seen that, setting, for sake of comparison, ωn2 = ωn, then the 2nd order type 1 loop is not practically slower than the 1st order loop!

“Slow or fast” in the sentences above means both:
- slow or fast to acquire the lock condition
- slow or fast to drift to its free running frequency when the input signal disappears.
The following figure contrasts the Unit Step Responses of the 3 important PLL models:
USRs of the 3 important loop models.
2 - 1 and 2 - 2 are plotted for natural undamped frequency = 6.28 Grad/sec and ζ = 1
1 -1 is plotted for both natural frequency = 6.28 Grad/sec and 3.14 Grad/sec.

Note that the USR of the 1 - 1 loop model is plotted for two different values of ωn1: ωn1 = ωn2 of the other two loops and 1/2 ωn1 = ωn2 of the other two loops

The example of the de-jitterizing stage[edit]

[7] [8]


  1. F.M.Gardner.....
  2. ITU-T Series G Supplement 36: Jitter and wander accumulation in digital networks
  3. ITU-T G8251 09/2010 The control of jitter and wander within the optical transport network (OTN), Annex A7: Jitter transfer
  4. ; Clock Recovery Primer, Part 2, Figure.21 Clock recovery in standards. and 10. Survey of Clock Recovery Used in Selected Standards.
  5. ITU-T G.813 (03/2003) Timing characteristics of SDH equipment slave clocks (SEC), Appendix II: Considerations on bandwidth requirements, noise accumulation and payload wander accumulation, II.1 Introduction.
  6.,%20Part%202 Clock Recovery Primer, Part 2 by Guy Foster, par.10: Survey of Clock Recovery Used in Selected Standards
  7. 1MA98: dB or not dB? Rohde & Schwarz Application Note
  8. Telecommunications: Glossary of Telecommunication Terms Federal Standard 1037C August 7, 1996

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