Microprocessor Design/Wire Wrap
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Historically, most of the early CPUs were built by attaching integrated circuits (ICs) to circuit boards and wiring them up.
Nowadays, it's much faster to design and implement a new CPU in a FPGA -- the result will probably run faster and use less power than anything spread out over multiple ICs.
However, some people still design and build CPUs the old-fashioned way. Such a CPU is sometimes called a "home brew CPU" or a "home built CPU".
Some people feel that physically constructing a CPU in this way, since it allows students to probe the inner workings of the CPU, it helps them "Touch the magic"[1], helps them learn and understand the underlying electronics and hardware.
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[edit] Overview
(FIXME: How do I get the picture from http://en.wikipedia.org/wiki/Image:YUNTEN.gif to show up here?)
A homebrew CPU is a central processing unit constructed using a number of simple integrated circuits, usually from the 7400 Series. When planning such a CPU, the designer must not only consider the hardware of the device but also the instructions the CPU will have, how they will operate, the bit patterns for each one, and their mnemonics. Before the existence of computer based circuit simulation many commercial processors from manufacturers such as Motorola were first constructed and tested using discrete logic (see Motorola 6809).
Although no limit exists on data bus sizes when constructing such a CPU, the number of components required to complete a design increases exponentially as bus size gets wider. Common physical data bus sizes are 1-bit, 4-bits, 8-bits, and 16-bits, although incomplete design documents exist for a 40-bit CPU.
A microcoded CPU may be able to present a significantly different instruction set to the application programmer than seems to be directly supported by the hardware used to implement it. For example, the 68000 presented a 32-bit instruction set to the application programmer -- a 32-bit "add" was a single instruction -- even though internally it was implemented with 16-bit ALUs.
For example, w:serial computers, even though they do calculations one bit per clock cycle, present a instruction set that deals with much wider words -- often 12 bits (PDP-14), 24 bits (D-17B), or even wider -- 39 bits (Elliott 803).
Notable Homebrew CPUs
The Magic-1 is a CPU with an 8-bit data bus and 16-bit address bus running at about 3.75MHz. [2]
The Mark I FORTH also has a 8-bit data bus and 16-bit address bus, but runs at 1MHz. [3]
The V1648CPU is a CPU with a 16-bit data bus and 48-bit address bus that is currently being designed. [4]
[edit] Parts
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[edit] Tools
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[edit] Design Tips
There are many ways to categorize CPUs. Each "way to categorize" represents a design question, and the various categories of that way represent various possible answers to that question that needs to be decided before the CPU implementation can be completed.
One way to categorize CPU that has a large impact on implementation is: "How many memory cycles will I hold one instruction before fetching the next instruction?"
- 0: load-instruction on every memory cycle (Harvard architecture)
- 1: At most 1 memory cycle between each load-instruction memory cycle ( load-store architecture )
- more: some instructions have 2 or more memory cycles between load-instruction memory cycles (memory-memory architecture)
Another way to categorize CPUs is "Will my control lines be controlled by a flexible microprogramming, a fixed control store, or by hard-wired control decoder that directly decodes the instruction?"
The load-store and memory-memory architectures require a "instruction register" (IR). At the end of every instruction (and after coming out of reset), the next instruction is fetched from memory[PC] and stored into the instruction register, and from then on the information in the instruction register (directly or indirectly) controls everything that goes on in the CPU until the next instruction is stored in the instruction register.
For homebrew CPUs, the 2 most popular architectures are[citation needed]:
- direct-decode Harvard architecture
- flexible microprogramming that supports the possibility of memory-memory architecture.
[edit] Harvard architecture
The simplest kinds of CPU control logic use the Harvard architecture. However, Harvard architecture requires 2 separate storage units -- the program memory and the data memory. Some Harvard architecture machines, such as "Mark's TTL microprocessor", don't even have an instruction register -- in those machines, the address in the program counter is always applied to the program memory, and the data coming out of the program memory directly controls everything that goes on in the CPU until the program counter changes. With these machines, storing new programs into the program memory becomes a bit tricky.
[edit] microcode architecture
See Microprocessor Design/Microcodes.
[edit] Assembly Tips
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[edit] Programming Tips
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[edit] Further Reading
- Harry Porter's Relay Computer (415 Relays, all identical 4PDT)
- "Relay Computer Two" by Jon Stanley (281 relays, of 2 types: 177 SPDT, and 104 4PDT)
- A Minimal TTL Processor for Architecture Exploration by Bradford J. Rodriguez (aka PISC, the Pathetic Instruction Set Computer)
- Wikipedia:Apollo Guidance Computer
- V1648: (16 bit data) (48 bit address bus?)
- "the Ultimate RISC" and "the Minimal CISC"
- alt.comp.hardware.homebuilt FAQ
- Mark's TTL microprocessor (uses only 8 chips ... "Without using the two PALs I used, it would be 16 chips.") (is there a better URL for this?)
- "Prehistoric Cpu's & Octal Amps" (18 bit data bus? 24 bit data bus?)
- other homemade CPUs
- yet more homemade CPUs
- "Viktor's Amazing 4-bit Processor" ... can re-program in-circuit using manual switches. About 90 chips.
- MT15 by Dieter Mueller is built almost entirely out of (around 3000) individual SMT transistors ... also has some essays on microprogramming and ALU design.
- LM3000 CPU designed and built by five students at Bennington College, Vermont, using fifty-three integrated circuits.
- The D16/M by John Doran is a 16-bit digital computer implemented with SSI and MSI HCMOS integrated logic and constructed using wire-wrap techniques. Its timing and control unit is microprogrammed (fully horizontal, with a 72-bit control word).
