Microprocessor Design/Microcode
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RISC units are typically faster and more efficient than CISC units. For this reason, many CISC processors have complicated instruction decoders that actually convert the CISC machine code into a RISC-like set of internal instructions known as microcodes. These microcodes are then fed into the internal core of the processor, which is based on the RISC design.
The most common way[citation needed] to implement memory-memory architecture CPUs (even with single-chip microprocessors, not just wire-wrapped machines) uses a small "control store" ROM. The output data bits of the control store drive a "pipeline register". The clock signal determining the cycle time of the system primarily clocks this pipeline register. The bits stored in the pipeline register directly control everything that goes on in the CPU.
Some of the bits in the pipeline register do nothing but drive some of the address bits of the control store. Those bits -- that sub-field of the pipeline register -- is sometimes called the "microprogram counter", even though it is merely a latch -- typically the control store is programmed such that those bits increment on every clock cycle, and reset to zero when a new instruction is loaded into the instruction register. The instruction register directly drives some of the address lines of the control store ROM. A few more address lines of the control store ROM are driven by status bits such as the Z flag and the C flag.
Some CPUs, such as the ECOMIPS[1], the Intel Core 2 and the Intel Xeon,[2] use "writable microcode" -- rather than storing the microcode in ROM or hard-wired logic, the microcode is stored in a RAM called a Writable Control Store or WCS.
[edit] further reading
- "Viktor's Amazing 4-bit Processor" has microcode that he says *could* have been implemented with about 90 diodes in a traditional diode matrix; but instead he implemented microcode with a Flash memory chip he can re-program in-circuit using manual switches.
- MT15 by Dieter Mueller uses transistors instead of diodes in a big AND-OR PLA (programmable logic array) matrix to implement the microcode.
- ↑ "ECOMIPS: An Economic MIPS CPU Design on FPGA" by Xizhi Li and Tiecai Li
- ↑ Wikipedia: microcode#Writable_control_stores
