Programmable Logic/VHDL Operators
This page is going to discuss VHDL Operators.
Some abbreviations used in this text:
- int - integer, a data type
- sl - std_logic, a data type (in most cases replacable with bit)
- slv - std_logic_vector, a data type (in most cases replacable with bit_vector)
- slu - std_logic_unsigned - a part of library ieee.
- sls - std_logic_signed - a part of library ieee.
- iff - "if and only if"
Contents
Logical Operators[edit]
This list is far from complete.
operator | examples | description |
---|---|---|
sl and sl | a_sl <= b_sl and c_sl a_sl <= ieee.std_logic_1164."and"(b_sl, c_sl); |
a_sl will be '1' iff both b_sl and c_sl is '1' |
slv and slv | a_slv <= b_slv and c_slv a_slv <= ieee.std_logic_1164."and"(b_slv, c_slv); |
Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits) |
sl or sl | a_sl <= b_sl or c_sl a_sl <= ieee.std_logic_1164."or"(b_sl, c_sl); |
a_sl will be '1' iff at least one of b_sl and c_sl is '1'. |
slv or slv | a_slv <= b_slv or c_slv a_slv <= ieee.std_logic_1164."or"(b_slv, c_slv); |
Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits) |
sl xor sl | a_sl <= b_sl xor c_sl a_sl <= ieee.std_logic_1164."xor"(b_sl, c_sl); |
a_sl will be '1' iff exactly one of b_sl and c_sl is '1'. |
slv xor slv | a_slv <= b_slv xor c_slv a_slv <= ieee.std_logic_1164."xor"(b_slv, c_slv); |
Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits) |
not sl | a_sl <= not b_sl a_sl <= ieee.std_logic_1164."not"(b_sl); |
a_sl will be inverse of b_sl, that is '1' iff b_sl = '0'. |
not slv | a_slv <= not b_slv a_slv <= ieee.std_logic_1164."not"(b_slv); |
Applied to each respectively bits in a_slv, b_slv. a_slv, b_slv must have equal length (e.g. 8 bits) |
sl nand sl | a_sl <= b_sl nand c_sl a_sl <= ieee.std_logic_1164."nand"(b_sl, c_sl); |
a_sl will be '1' iff at least one of b_sl and c_sl is '0'. Equivalent to not (sl and sl) |
slv nand slv | a_slv <= b_slv nand c_slv a_slv <= ieee.std_logic_1164."nand"(b_slv, c_slv); |
Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits) |
sl nor sl | a_sl <= b_sl nor c_sl a_sl <= ieee.std_logic_1164."nor"(b_sl, c_sl); |
a_sl will be '1' iff both b_sl and c_sl is '0'. Equivalent to not (sl or sl) |
slv nor slv | a_slv <= b_slv nor c_slv a_slv <= ieee.std_logic_1164."nor"(b_slv, c_slv); |
Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits) |
sl xnor sl | a_sl <= b_sl xnor c_sl a_sl <= ieee.std_logic_1164."xnor"(b_sl, c_sl); |
a_sl will be '1' iff both b_sl and c_sl is either '1' or '0'. Equivalent to not (sl xor sl) |
slv xnor slv | a_slv <= b_slv xnor c_slv a_slv <= ieee.std_logic_1164."xnor"(b_slv, c_slv); |
Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits) |
Arithmetic Operators[edit]
Relational Operators[edit]
Shift and Rotate[edit]
This page or section is an undeveloped draft or outline. You can help to develop the work, or you can ask for assistance in the project room. |
Operators[edit]
Sign Operators[edit]
Sign operators are unary operators, i.e. have only one, right operand, which must be of a numeric type. The result of the expression evaluation is of the same type as the operand. There are two sign operators (Table 12).
Table 12 : Sign operators :
+ | Identity |
- | Negation |
When ( + ) sign operator is used, the operand is returned unchanged, but In case of ( - ) sign operator the value of operand with the negated sign is returned. Because of the lower priority, the sign operator in the expression cannot be directly preceded by the multiplication operator, the exponentiation operator (**) or the abs and not operators. When these operators are used then sign operator and its operand should be enclosed in parentheses (Example 7).
Multiplying Operators[edit]
The multiplication and division operators are predefined for all integers, floating point numbers. Under certain conditions, they may be used for operations on physical type objects as well. The mod and rem operators, on the other hand, are defined only for the integers. When mod and rem operators are used, then both the operands and the result are of the same integer type. The multiplying operators are shown in the Table 13.
Table 13. Multiplying operators
* | Multiplication |
/ | Division |
mod | Modulus |
rem | Remainder |
Miscellaneous operators[edit]
The two miscellaneous operators are shown in the Table 14.
Table 14. Miscellaneous operators
** | Exponentiation |
abs | Absolute value |
The abs operator has only one operand. It allows defining the operand's absolute value. The result is of the same type as the operand.
The exponentiation operator has two operands. This operator is defined for any integer or floating point number. The right operand (exponent) must be of integer type. When the exponent is the positive integer, then the left operand is repeatedly multiplied by itself. When the exponent is the negative number, then the result is a reverse of exponentiation with the exponent equal to the absolute value of the right operand (Example 9). If the exponent is equal to 0 the result will be 1.
Examples[edit]
Example 1[edit]
v := a + y * x;
The multiplication y*x is carried out first, then a is added to the result of multiplication. This is because the multiplication operator has higher level of priority than the adding operator.
Example 2[edit]
variable We1, We2, We3, Wy : BIT := '1';
Wy := We1 and We2 xnor We1 nor We3;
For the initial value of the variables We1, We2, We3 equal to '1', the result is assigned to the variable Wy and is equal to '0'.
Example 3[edit]
variable Zm1: REAL := 100.0;
variable Zm2 : BIT_VECTOR(7 downto 0) := ('0','0','0','0','0','0','0','0');
variable Zm3, Zm4 : BIT_VECTOR(1 to 0);
Zm1 /= 342.54 -- True
Zm1 = 100.0 -- True
Zm2 /= ('1', '0', '0', '0', '0', '0', '0', '0') -- True
Zm3 = Zm4 -- True
Example 4
Zm1 > 42.54 -- True
Zm1 >= 100.0 -- True
Zm2 < ('1', '0', '0', '0', '0', '0', '0', '0') -- True
Zm3 <= Zm2 -- True
Example 5[edit]
variable Zm5 : BIT_VECTOR(3 downto 0) := ('1','0','1','1');
Zm5 sll 1 -- ('0', '1', '1', '0')
Zm5 sll 3 -- ('1', '0', '0', '0')
Zm5 sll -3 -- Zm5 srl 3
Zm5 srl 1 -- ('0', '1', '0', '1')
Zm5 srl 3 -- ('0', '0', '0', '1')
Zm5 srl -3 -- Zm5 sll 3
Zm5 sla 1 -- ('0', '1', '1', '1')
Zm5 sla 3 -- ('1', '1', '1', '1')
Zm5 sla -3 -- Zm5 sra 3
Zm5 sra 1 -- ('1', '1', '0', '1')
Zm5 sra 3 -- ('1', '1', '1', '1')
Zm5 sra -3 -- Zm5 sla 3
Zm5 rol 1 -- ('0', '1', '1', '1')
Zm5 rol 3 -- ('1', '1', '0', '1')
Zm5 rol -3 -- Zm5 ror 3
Zm5 ror 1 -- ('1', '1', '0', '1')
Zm5 ror 3 -- ('0', '1', '1', '1')
Zm5 ror -3 -- Zm5 rol 3
Example 6[edit]
constant B1: BIT_VECTOR := "0000"; -- four element array
constant B2: BIT_VECTOR := "1111"; -- four element array
constant B3: BIT_VECTOR := B1 & B2; -- eight element array, ascending
-- direction, value "00001111"
subtype BIT_VECTOR_TAB is BIT_VECTOR (1 downto 0);
constant B4: BIT_VECTOR_TAB := "01";
constant B5: BIT_VECTOR:= B4 & B2; -- six element array, descending
-- direction, value "011111"
constant B6 : BIT := '0' ;
constant B7 : BIT_VECTOR := B2 & B6;-- five element array, ascending
-- direction, value "11110"
constant B8: BIT := '1';
constant B9: BIT_VECTOR := B6 & B8; -- two element array, ascending
-- direction value "01"
Example 7[edit]
z := x * ( -y) -- A legal expression
z := x / (not y) -- A legal expression
The same expressions without parentheses would be illegal.
Example 8[edit]
variable A,B :Integer;
variable C : Real;
C:= 12.34 * ( 234.4 / 43.89 );
A:= B mod 2;
Example 9[edit]
2 ** 8 = 256
3.8 ** 3 = 54.872
4 ** (-2) = 1 / (4**2) = 0.0625
Important Notes[edit]
- All predefined operators for standard types are declared in the package STANDARD.
- The operator not is classified as a miscellaneous operator only for the purpose of defining precedence. Otherwise, it is classified as a logical operator.