Unit 1.1.1 Structure and Function of the Processor
- 1 ALU, CU & Registers - 3 Distinct CPU Elements
- 2 The FDE Cycle
- 3 Factors Affecting CPU Performance
ALU, CU & Registers - 3 Distinct CPU Elements
Arithmetic and Logic Unit (ALU) - A vast array of logic gates, this component deals with basic arithmetic such as binary addition or subtraction. It is capable of many complex mathematical functions, for example sine, cosine and floating point division.
Control Unit (CU) - A component that co-ordinates the various units inside the processor via the use of "control signals" which determine the flow of data into and around the processor. Instructions are decoded in the Control unit during the FDE cycle.
• Name: Control unit
• Explanation: Fetches each instruction in sequence, decodes and synchronises it before executing it by sending control signals to other parts of the computer.
• Name: Arithmetic Logic Unit (Accept ALU)
• Explanation: The processing and manipulation of data which normally consists of arithmetic operations or logical comparisons, allowing a program to take decisions.
- A location where a single item of data can be stored.
- They are specialist high-speed storage areas contained inside the CPU.
- Before any data can be processed, it must first be represented in a register.
- e.g. Before any two numbers can be multiplied, they must both be represented in individual registers.
Registers located in the processor:
- Program Counter (PC) - Contains the address of the next instruction to be executed.
- Memory Address Register (MAR) - Contains the address of the memory location currently in use.
- Memory Data Register (MDR) - Contains instructions/data to be executed.
- Current Instruction Register (CIR) - Holds the instruction whilst it is decoded.
- Accumulator (ACC) - Stored the results of calculations processed by the CPU (ALU).
Reason for the CIR and MDR: It may seem as though the CIR and MDR always hold the same value. However, consider an input instruction. If there were no CIR, the MDR would hold the input instruction. However, when the data is input, the inputted value would overwrite the input instruction in the MDR hence the need for the CIR and the MDR.
Buses are a collection of wires through which data is transmitted from one part of a computer to another. These typically include:
- Data Bus - The path along which data is transmitted, usually between the CPU and memory. This is a half-duplex pathway; data can travel in either direction but only one at a time.
- Address Bus - When data is saved to/loaded from memory, the address of the memory location to which it must be stored/loaded from must also be sent. The address always travels along the address bus. This is a simplex pathway; the CPU only ever sends the memory address, it never receives one from the memory.
- Control Bus - The Control Unit sends and receives signals from all parts of the computer, ensuring all the processes occur at the correct time, in the correct order. These signals travel along the control bus which is made up of several control lines including an interrupt-request line, a memory read line and a memory write line in addition to the clock for synchronizing operations.
The FDE Cycle
This cycle describes the standard steps needed for processing to take place.
- The Address in the Program Counter is copied to the Memory Address Register.
- The Program Counter is incremented.
- A Fetch signal is sent along the Control Bus by the Control Unit to the Memory, while the address held in the Memory Address Register is sent to the Memory along the Address Bus. The value stored in memory returns to the CPU along the Data Bus and is held in the Memory Data Register.
- This value in the Memory Data Register is copied to the Current Instruction Register.
- The contents of the Current Instruction Register are sent to the Control Unit for decoding.
- The type of addressing used by the instruction must be identified:
- If the address is a direct address, load this address into the Memory Address Register and retrieve the contents of that address.
- If the address is an indexed address, add the contents of the index register to the address, then copy this value to the Memory Address Register. Retrieve the contents of this memory location.
- If the instruction is a jump:
- Load the address operand into the Program Counter and copy the address component in the Current Instruction Register to the Program Counter.
- At this point execution has finished
- Otherwise, execute the instructions.
- PC 0010;
- MAR 0001;
- MBR 00100100;
- The Instruction is held in the CIR // instruction in CIR is decoded;
- The control unit/instruction decoder decodes the instruction;
- Instruction will be split into opcode and operand;
- Relevant part of processor/CPU executes instruction // using ALU to perform calculations;
- Further memory fetches/saves carried out if required;
- Result of computation stored in accumulator/registertwritten to main memory;
- Status register updated,If jump/branch instruction PC is updated;
c)The current value in the accumulator would be stored in (memory) address,'locauon 0011/3; Number 011/3 stored in (memory) address/location 0011/3;
Factors Affecting CPU Performance
The performance of a CPU can be affected by 4 different quantities:
The clock speed of the processor is the number of FDE Cycles it can perform per second, for example 3.4 GHz is 3,400,000,000 cycles per second. The higher the clock speed, the greater the number of FDE Cycles that can occur each second, hence higher clock speeds improve performance.
Cache Memory is memory which is built directly into the CPU. It is far faster to access than RAM, as it is much closer to the registers that require the data, and it also operates at a similar speed to the CPU, so has very little lag comparative to retrieving data from RAM. It contains multiple levels of cache which differ in size and distance from the CPU, Level 1, 2 and 3 cache. Level 1 is closest to the CPU and is the smallest, whereas Level 3 is furthest from the CPU and is the biggest. The reason all the cache isn't simply made Level 1 is cost- faster memory is more expensive.
Frequently used data such as parts of the OS are stored in the cache, allowing the processor to run faster as it doesn't have to rely on slower fetches from the RAM as often.
Number of Cores
A multi-core processor is one which contains multiple distinct processing units within a single CPU. Each core can operate independently of the others, and will each have their own low level cache, as well as sharing a high level cache. Different cores can run different applications at the same time during multitasking, allowing more actions to occur each second.
However, multiple cores do not always improve processor performance; if a core is processing an instruction which is dependent on the outcome of another instruction, being processed by another core, it will have to wait until that core returns a result before the instruction can finish processing. This can cause hanging, where a core is wasted while it waits for the result of another instructions execution.
Pipelining is a process that can be used to improve the performance of a CPU. It operates in such a way that whilst the processor is decoding an instruction, the next instruction can be fetched from memory. This works best in code where the next instruction is not dependent on the instruction before it- when code branches, the CPU will have decoded the wrong next instruction and so will have to 'clear the pipes' by getting rid of the current fetch and decode steps.
|Step 1||Instruction 1|
|Step 2||Instruction 2||Instruction 1|
|Step 3||Instruction 3||Instruction 2||Instruction 1|
|Step 4||Instruction 4||Instruction 3||Instruction 2|
Additional factors affecting performance
- Multithreading capabilities
- Bus width
- Register size
4 marks, 2 for identifying the features and 2 for the explanations. Maximum of 2 marks per feature. Only mark the first two features.
- Add a multi-core processor.
- Each core can carry out two fetch-decode-execute (FDE) cycles simultaneously.
- A task can be split between the cores for execution.
- Add a processor with a faster clock speed.
- The processor can complete more FDE cycles per second.
- Add more RAM.
- The processor can have more software and files open simultaneously.
There are 2 main architectures that our syllabus is concerned with - Von Neumann and Harvard:
This architecture has a single control unit and a single address, data and control bus. It works sequentially through instructions, and stores instructions and data together in the same memory unit. It cannot fetch multiple instructions at the same time as data is sent along a single bus - this is known as a von Neumann bottleneck. Instructions are carried out in two clock cycles (decode and execute).
This architecture is almost identical to Von Neumann, however it stores data and instructions in separate memory units. The CPU is also capable of reading an instruction and performing memory access at the same time, even without a cache. This is because there are separate buses for the data and instructions. It is possible to use Pipelining in Harvard architecture as it has separate memory for instruction and data with separate buses - if pipelining is used, instructions are carried out in a single clock cycle.
This is a modified form of Harvard Architecture. It relaxes the strict separation of data and instructions, and still lets the CPU access more than 2 memory buses.
The architecture uses the stored program concept (1). Answers should also include an explanation of the fetch-decode-execute cycle (2).