VHDL for FPGA Design/T Flip Flop

From Wikibooks, open books for an open world
< VHDL for FPGA Design
Jump to: navigation, search

Synchronous Positive edge T Flip-Flop with Reset and Clock enable[edit]

library IEEE;
entity T_FF_VHDL is
   port( T: in  std_logic;
         Reset: in std_logic;
         Clock_enable: in std_logic;
         Clock: in std_logic;
         Output: out std_logic);
end T_FF_VHDL;
architecture Behavioral of T_FF_VHDL is
   signal temp: std_logic;
   process (Clock) 
      if Clock'event and Clock='1' then 		
         if Reset='1' then   
            temp <= '0';
         elsif Clock_enable ='1' then
 	    if T='0' then
 	       temp <= temp;
 	    elsif T='1' then
 	       temp <= not (temp);
 	    end if;
         end if;
      end if;
   end process;
   Output <= temp;
end Behavioral;

Simulation Results[edit]

 TFF Final.png

Generated Symbol[edit]

 File:T FF SCH F.png