VHDL for FPGA Design/Decoder

From Wikibooks, open books for an open world
Jump to: navigation, search

Decoder.PNG

Decoder VHDL Code[edit]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
 
entity Decoder is
   port(E : in std_logic;
        din : in std_logic_vector(2 downto 0);
        dout : out std_logic_vector(7 downto 0));
end Decoder;
 
architecture descript of Decoder is
begin
 
   dout <="00000000" when E='1' else
        "00000001" when E='0' and din="000" else
        "00000010" when E='0' and din="001" else
        "00000100" when E='0' and din="010" else
        "00001000" when E='0' and din="011" else
        "00010000" when E='0' and din="100" else
        "00100000" when E='0' and din="101" else
        "01000000" when E='0' and din="110" else
        "10000000" when E='0' and din="111";
 
end descript;

Simulation Waveform[edit]

Decoder fin.png

See Also[edit]