VHDL for FPGA Design/Decoder

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity Decoder is
   Port(Sel: in std_logic_vector(2 downto 0);
          y: out std_logic_vector(7 downto 0));
end Decoder;
 
architecture beh of Decoder is
begin
   y <= "00000001" when Sel="000" else
        "00000010" when Sel="001" else
        "00000100" when Sel="010" else
        "00001000" when Sel="011" else
        "00010000" when Sel="100" else
        "00100000" when Sel="101" else
        "01000000" when Sel="110" else
        "10000000";
end beh;