VHDL for FPGA Design/4-Bit Multiplier

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity Multiplier_VHDL is
   port( Nibble1, Nibble2: in std_logic_vector(3 downto 0);
         Result: out std_logic_vector(7 downto 0));
end Multiplier_VHDL;
 
architecture Behavioral of Multiplier_VHDL is
begin
   Result <= Nibble1 * Nibble2;
end Behavioral;