VHDL for FPGA Design/4-Bit Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity Adder is
   port( nibble1,nibble2: in std_logic_vector(3 downto 0); 
         Sum: out std_logic_vector(3 downto 0); 
         Carry_out: out std_logic);
end Adder;
 
architecture Behavioral of Adder is
   signal temp: std_logic_vector(4 downto 0); 
begin 
   temp <= conv_std_logic_vector( (conv_integer(nibble1) +  conv_integer(nibble2)),5); 
   --- OR use the following syntax:
   -- temp <= ('0' & nibble1) + ('0' & nibble2);
   Sum <= temp(3 downto 0); 
   Carry_out  <= temp(4);
end Behavioral;