VHDL for FPGA Design/4-Bit ALU

 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity ALU_VHDL is
   port( Carry_Out: out std_logic;
	 Flag: out std_logic;
	 Nibble1: in std_logic_vector(3 downto 0);
	 Nibble2: in std_logic_vector(3 downto 0);
	 Operation: in std_logic_vector(2 downto 0);
	 result: out std_logic_vector(3 downto 0));
end ALU_VHDL;
 
architecture Behavioral of ALU_VHDL is
   signal temp: std_logic_vector(4 downto 0);
begin
   process(Nibble1,Nibble2,Operation,temp)
   begin
      Flag <= '0';
      case Operation is 
 	 when "000" => -- res = nib1 + nib2, flag = carry = overflow
 	    temp <= conv_std_logic_vector((conv_integer(Nibble1) + conv_integer(Nibble2)),5);
            result <= temp(3 downto 0);
 	    Flag <= temp(4);
 	 when "001" => -- res = |nib1 - nib2|, flag = 1 iff nib2 > nib1
 	    if Nibble1 >= Nibble2 then
 	       result <= Nibble1 - Nibble2;
 	       Flag <= '0';
            else
 	       result <= Nibble2 - Nibble1;
 	       Flag <= '1';
            end if;
 	 when "010" =>
 	    result <= Nibble1 and Nibble2;
 	 when "011" =>
 	    result <= Nibble1 or Nibble2;
 	 when "100" =>
 	    result <= Nibble1 xor Nibble2;
 	 when "101" =>
 	    result <= not Nibble1;
  	 when "110" =>
            result <= not Nibble2;
 	 when others => -- res = nib1 + nib2 + 1, flag = 0
 	    temp <= conv_std_logic_vector((conv_integer(Nibble1) + conv_integer(not Nibble2)) + 1,  5);
 	    result <= temp(3 downto 0);
 	    Flag <= temp(4);
      end case;
   end process;
end Behavioral;