Programmable Logic/VHDL Sequential Statement

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Sequential statements are used in processes to specify how signals are assigned. The process is executed in order as a whole. After all the sequential statements in the process are executed the signals are assigned their new values.

[edit] Assignment

A signal is assigned as follows:

sQ <= sQ_next;

This statement can be read as "assign sQ the value of sQ_next on the next simulation cycle.

[edit] IF Statements

If statements allow for the conditional assignment of signals or variables in a process. An example of an if statement is as follows. If statements are structured very similarly to a typical sequential language.

if(sQ = '1' and sR = '1') then
    sQ_next <= '0';
    sR_next <= '0';
elsif(sQ = '0' and sR = '0') then
    sQ_next <= '1';
    sR_next <= '1';
else
    sQ_next <= '1';
    sR_next <= '1';
end if;

If-Elsif statements are usually synthesized as a chain of priority encoded multiplexers. Large if-elsif chains can produce many layers of logic when synthesized and cause problems when implementing on devices (in particular FPGAs). When a choice between many options is needed it is often more beneficial to use a "case" statement, which is typically synthesized as one large mux rather than a chain of priority encoded muxes.

[edit] CASE Statements

A case statement is a way to describe a conditional assignment with a large number of choices.

architecture behavioral of Question1 is
begin
    process(D)
    begin
        case D is
            when "0000" | "1110" =>
                Y <= "0011";		
            when "0001" | "0100" | "0101" | "0110" | "0111" | "1010" | "1011" | "1100" | "1111" =>
                Y <= "0000";
            when "0010" | "1001" =>
                Y <= "0110";
            when "0011" | "1101" =>
                Y <= "1100";
            when "1000" =>
                Y <= "1001";
            when others =>
                null;
        end case;
    end process;
end architecture behavioral;

Case statements are often synthesized as multiplexers.

[edit] LOOP Statements