Programmable Logic/VHDL Sequential Statement
Sequential statements are used in processes to specify how signals are assigned. The process is executed in order as a whole. After all the sequential statements in the process are executed the signals are assigned their new values.
Assignment[edit | edit source]
A signal is assigned as follows:
sQ <= sQ_next;
This statement can be read as "assign sQ the value of sQ_next on the next simulation cycle.
So far, in the if statements only signals were used. The same rules apply when using variables, with a single difference. Like a signal, if a variable is assigned to only in some branches of the if statement, then the previous value is preserved by feedback. Unlike the case when a signal is used, the reading and writing of a variable in the same process will result in feedback only if the read occurs before the write. In this case, the value read is the previous value of the variable. In the case when a signal is used, a read and a write in the same process will always result in feedback. This observation may be used to create registers or counters using variables. Remember that a sequential process is interpreted by synthesis by placing a flip-flop or register on every signal assigned to in the process. This means that normally variables are not written to flip-flops or registers. However, if there is feedback of a previous variable value, then this feedback is implemented via a flip-flop or register to make the process synchronous. Example 6.21 describes a counter using the unsigned integer type. When a value of type unsigned is incremented, if the value is the highest value of the range, then the lowest value of the range is obtained.
process variable count: unsigned (7 downto 0); begin wait until clk = '1'; if reset = '1' then count := "00000000"; else count := count + 1; end if; result <= count; end process;
In this example, in the else branch of the if statement the previous value of the count variable is being read to calculate the next value. This results in a feedback. Note that in this example actually two registers are created. According to the feedback rules, variable count will be registered. Signal result will also be registered, because all signals assigned to in a sequential process will be registered. This extra register will always contain the same value as the register for variable count. The synthesis tool will normally eliminate this redundant register.
CASE Statements[edit | edit source]
A case statement is a way to describe a conditional assignment with a large number of choices.
architecture behavioral of Question1 is begin process(D) begin case D is when "0000" | "1110" => Y <= "0011"; when "0001" | "0100" | "0101" | "0110" | "0111" | "1010" | "1011" | "1100" | "1111" => Y <= "0000"; when "0010" | "1001" => Y <= "0110"; when "0011" | "1101" => Y <= "1100"; when "1000" => Y <= "1001"; when others => null; end case; end process; end architecture behavioral;
Case statements are often synthesized as multiplexers.