4024 7-bit (÷128) ripple counter The 4024 is a ripple counter so beware that glitches may occur in any logic gate systems connected to its outputs due to the slight delay before the later counter outputs respond to a clock pulse. The count advances as the clock input becomes low (on the falling-edge), this is indicated by the bar over the clock label. This is the usual clock behaviour of ripple counters and it means a counter output can directly drive the clock input of the next counter in a chain. Output Qn is the nth stage of the counter, representing 2n, for example Q4 is 24 = 16 (1/16 of clock frequency) and Q7 is 27 = 128 (1/128 of clock frequency). The reset input should be low for normal operation (counting). When high it resets the count to zero (all outputs low).