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- Chip Design Made Easy
- MIPS Assembly
- SPARC Assembly
- Programmable Logic
- Digital Circuits
- Parallel Computing and Computer Clusters
- Floating Point
- Embedded Control Systems Design/Processors
- Embedded Systems/Microprocessor Architectures
- Floating Point/Floating Point Hardware
- Wikipedia:CPU design
- Wikipedia:Instruction set
- Apollo Guidance Computer
- Wikipedia:soft microprocessor discusses FPGA CPUs
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- "homebrew CPU".
- Knowledge and Concepts of VLSI Chip Design and Development
- "Great moments in microprocessor history" by W. Warner 2004
- Daniel J. Sorin has some good notes online for classes he's taught: "ECE 152: Introduction to Computer Architecture" and "ECE 252 / CPS 220: Advanced Computer Architecture I".
- Jacob Nelson has some information online about his microprocessor designs: "An FPGA-based Custom Computer" and "The uToad Proof of Concept", both reminiscent of the PDP-10.
- OpenCores has many open-hardware FPGA and CPLD designs under development, including dozens of microprocessors. These include entirely new processors such as "JOP: a Java Optimized Processor", "ZPU - the worlds smallest 32 bit CPU with GCC toolchain", the "OpenRISC 1000", "MCPU ... fits into a 32 Macrocell CPLD". These also include processors designed to be software compatible with ("clean-room re-implementations of") several older proprietary processors -- MIPS, ARM, x86, AVR, PIC, 68HC11, 68000, Alpha, etc.
- The Am1601 is a stack based CPU implemented in a FPGA. It is designed to be radiation tolerant.
- VHDL Source Code for Simple 8-bit CPU
- "Microprocessor Architectures" has a "Java based simulator of a pipelined processor. ... The Java code is written in a style to simplify the process of converting the processor into a ... a FPGA implementation."
- "CPU Design HOW-TO" by Alavoor Vasudevan 2002
- The Advanced Processor Technologies Group at Manchester has microprocessor design and synthesis tools you can download and use.
- "The “high-level CPU” challenge" and "“High-level CPU”: follow-up" by Yossi Kreinin (and attached comments by a variety of other people) has some interesting ideas on CPU design.
- YASEP means "Yet Another Small Embedded Processor" by Yann Guidon: RTL source code is in VHDL, currently targeting the Actel ProASIC3 FPGA; simulator, an assembler, a disassembler, a manual, a development tool, all available for download (open source).
- StackOverflow: How does an assembly instruction turn into voltage changes on the CPU? -- good book recommendations, and an attempt to briefly summarize what this book is all about.
- Stackexchange: "A fun book to learn computer architecture" lists a few books on computer architecture and CPU design.
- Stackexchange: "Readable and educational implementations of a CPU in a HDL"
- Non-Von1 in a Spartan3E-1200 FPGA board
- Homebrew Cray-1A on a Xilinx Spartan-3E 1600 FPGA development board: built into a 1/10 scale model.
- fpga-cpu : FPGA CPU and SoC discussion list: list is for discussion of the design and implementation of field-programmable gate array based processors and integrated systems. It is also for discussion and community support of the XSOC Project.
- "Elementary Microprocessor ... The EM is intended as a simple microprocessor for educational purposes for those of us who are interested in learning not just what a CPU does, but *exactly how* a CPU works"
- The original EM was designed on the open-source Logisim digital logic simulator.
- Michael A. Morris. "M65C02 Microprocessor Core". An implementation in Verilog that supports the full instruction set of the W65C02.
- Steve Chamberlin. "Tiny CPU in a CPLD". Originally designed to fit into two very small CPLD chips -- both Altera EPM7128, which has 128 macrocells -- but actually constructed with a single Altera Max II EPM570 CPLD, which has roughly 440 macrocells, on a custom PCB. The program counter and "absolute" addresses are 10 bits, but bank switching allows programs and data to share a full uniform 64 KByte address space. Verilog source code available.
- Zach Metzinger. "The Toro Clock Project". Built in 1997. A clock based on an 8-bit CPLD-implemented custom CPU. The TORO processor was originally intended to fit on 5 PALCE22V10s; this implementation of the processor uses one 22V10 (instruction decoder) and one MACH211 (roughly equivalent to 4 22V10; ALU, program counter, and the accumulator); a multiplexed address and data bus ... bank switching ...
- HORNET is a highly configurable, cycle-level multicore simulator with support for power and thermal modeling. HORNET software uses several cores when run on multicore host hardware, and it supports simulating chips with over 100 cores. Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan and Srinivas Devadas, "Scalable, accurate multicore simulation in the 1000-core era".
- Patterson and Hennessy, Computer Organization and Design, 3rd Edition, Morgan Kaufmann, 2005. ISBN 1558606041
- ... should we list the other design books recommended by John Doran ? ...
- Nisan and Schocken. "The Elements of Computing Systems: Building a Modern Computer from First Principles". 2005. ISBN 978-0262640688. 
- Shimon Schocken. "From NAND to Tetris in 12 steps: building a modern computer from first principles"  is an overview of the Nisan and Schocken book.
- Hamacher, Vranesic, Zaky, Manjikian. "Computer Organization and Embedded Systems". ISBN 978-0073380650