Daniel J. Sorin has some good notes online for classes he's taught: "ECE 152: Introduction to Computer Architecture" and "ECE 252 / CPS 220: Advanced Computer Architecture I".
Jacob Nelson has some information online about his microprocessor designs: "An FPGA-based Custom Computer" and "The uToad Proof of Concept", both reminiscent of the PDP-10.
OpenCores has many open-hardware FPGA and CPLD designs under development, including dozens of microprocessors. These include entirely new processors such as "JOP: a Java Optimized Processor", "ZPU - the worlds smallest 32 bit CPU with GCC toolchain", the "OpenRISC 1000", "MCPU ... fits into a 32 Macrocell CPLD". These also include processors designed to be software compatible with ("clean-room re-implementations of") several older proprietary processors -- MIPS, ARM, x86, AVR, PIC, 68HC11, 68000, Alpha, etc.
The Am1601 is a stack based CPU implemented in a FPGA. It is designed to be radiation tolerant.
"Microprocessor Architectures" has a "Java based simulator of a pipelined processor. ... The Java code is written in a style to simplify the process of converting the processor into a ... a FPGA implementation."
YASEP means "Yet Another Small Embedded Processor" by Yann Guidon: RTL source code is in VHDL, currently targeting the Actel ProASIC3 FPGA; simulator, an assembler, a disassembler, a manual, a development tool, all available for download (open source).
"Elementary Microprocessor ... The EM is intended as a simple microprocessor for educational purposes for those of us who are interested in learning not just what a CPU does, but *exactly how* a CPU works"
The original EM was designed on the open-source Logisim digital logic simulator.
Steve Chamberlin. "Tiny CPU in a CPLD". Originally designed to fit into two very small CPLD chips -- both Altera EPM7128, which has 128 macrocells -- but actually constructed with a single Altera Max II EPM570 CPLD, which has roughly 440 macrocells, on a custom PCB. The program counter and "absolute" addresses are 10 bits, but bank switching allows programs and data to share a full uniform 64 KByte address space. Verilog source code available.
Zach Metzinger. "The Toro Clock Project". Built in 1997. A clock based on an 8-bit CPLD-implemented custom CPU. The TORO processor was originally intended to fit on 5 PALCE22V10s; this implementation of the processor uses one 22V10 (instruction decoder) and one MACH211 (roughly equivalent to 4 22V10; ALU, program counter, and the accumulator); a multiplexed address and data bus ... bank switching ...
HORNET is a highly configurable, cycle-level multicore simulator with support for power and thermal modeling. HORNET software uses several cores when run on multicore host hardware, and it supports simulating chips with over 100 cores. Mieszko Lis, Pengju Ren, Myong Hyon Cho, Keun Sup Shim, Christopher W. Fletcher, Omer Khan and Srinivas Devadas, "Scalable, accurate multicore simulation in the 1000-core era".