Microprocessor Design/FPU

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Similar to the ALU is the Floating-Point Unit, or FPU. The FPU performs arithmetic operations on floating point numbers.

An FPU is complicated to design, although the IEEE 754 standard helps to answer some of the specific questions about implementation. It isn't always necessary to follow the IEEE standard when designing an FPU, but it certainly does help.

Floating point numbers[edit | edit source]

This section is just going to serve as a brief refresher on floating point numbers. For more information, see the Floating Point book.

Floating point numbers are specified in two parts: the exponent (e), and the mantissa (m). The value of a floating point number, v, is generally calculated as:

IEEE 754[edit | edit source]

IEEE 754 format numbers are calculated as:

The mantissa, m, is "normalized" in this standard, so that it falls between the numbers 1.0 and 2.0.

Floating Point Multiplication[edit | edit source]

Multiplying two floating point numbers is done as such:

Likewise, division can be performed by:

To perform floating point multiplication then, we can follow these steps:

  1. Separate out the mantissa from the exponent
  2. Multiply (or divide) the mantissa parts together
  3. Add (or subtract) the exponents together
  4. Combine the two results into the new value
  5. Normalize the result value (optional).

Floating Point Addition[edit | edit source]

Floating point addition—and by extension, subtraction— is more difficult than multiplication. The only way that floating point numbers can be added together is if the exponents of both numbers are the same. This means that when we add two numbers together, we need first to scale the numbers so that they have the same exponent. Here is the algorithm:

  1. Separate the mantissa from the exponent of each number
  2. Compare the two exponents, and determine the difference between them.
  3. Add the difference to the smaller exponent, to make both exponents the same.
  4. Logically right-shift the mantissa of the number with the smaller exponent a number of spaces equal to the difference.
  5. Add the two mantissas together
  6. Normalize the result value (optional).

Floating Point Unit Design[edit | edit source]

As we have seen from the two algorithms above, an FPU needs the following components:

For addition/Subtraction
  • A comparator (subtractor) to determine the difference between exponents, and to determine the smaller of the two exponents.
  • An adder unit to add that difference to the smaller exponent.
  • A shift unit, to shift the mantissa the specified number of spaces.
  • An adder to add the mantissas together
For multiplication/division
  • A multiplier (or a divider) for the mantissa part
  • An adder for the exponent parts.

Both operation types require a complex control unit.

Both algorithms require some kind of addition/subtraction unit for the exponent part, so it seems likely that we can use just one component to perform both tasks (since both addition and multiplication won't be happening at the same time in the same unit). Because the exponent is typically a smaller field than the mantissa, we will call this the "Small ALU". We also need an ALU and a multiplier unit to handle the operations on the mantissa. If we combine the two together, we can call this unit the "Large ALU". We can also integrate the fast shifter for the mantissa into the large ALU.

Once we have an integer ALU designed, we can copy those components almost directly into our FPU design.

Further Reading[edit | edit source]