Microprocessor Design/Basic Theory

This basic theory of microchip briefly describes the microchip's architecture by using a "goods truck analogy".

We can imagine the whole microchip itself as a giant city. The city itself imports goodies from Input and exports those goodies to the Outputs. In the city, there are many highways running between various points of interest to process those goodies before exporting them again.

Clocking Speed

The first limit is obviously the speed of the delivery trucks. If the trucks can deliver faster, it will also deliver a lot more goodies across the city—say 2.0 million tonnes of goods per year (think of a million tonnes as 1 Ghz, thereby making this 2 Ghz) compared to 2.5 million tonnes of goods per year (again, think of this in terms of 2.5Ghz). Since the trucks are moving faster in the city with 2.5 million tonnes of gross product, they are processing more goods; a microprocessor is analogous.

However, there is a limit to how fast a delivery truck can drive on the highway; if the driver goes too fast, they might lose some of their cargo unexpectedly, or they might even crash. So, the speed of a single delivery truck is limited by the safety of the road. (Think of this as clocking speed)

CPU Fabrications

There are ways to make the highway safer such as by making all the turns wider, constructing guardrails, making the asphalt smoother, ensuring there are no debris on the road, and so on. When these techniques are employed, one can safely increase the maximum speed of the delivery trucks.

By using new fabrication processes, you can fit more transistors in a given space, which in turn gives you the space needed to implement a lot more complicated logical structures. Also, any contaminants that land on the wafer will damage the chips, which explains why the chips are manufactured in “clean rooms” (which, naturally, are very clean and have low concentrations of contaminants).

Pipelining

If there is one truck operating across the city, this truck must return before it can fulfill more pending deliveries. Therefore, the more trucks there are in standby, the faster the delivery process and thus the lesser the waiting time.

This is analogous to pipelining where the different tasks a processor has to carry out are split into separate "jobs", and when an instruction moves from one piece of the pipeline to the next, a new instruction can be started before the first instruction is totally finished.

Multi Cores

A four-lane road can carry more trucks than a single-lane road. If the one lane is busy, the other 3 lanes can share the traffic load simultaneously to prevent a traffic jam. Certain lanes can also be used for different purposes, like how an inside lane is used for cruising and an outside lane is used for exiting.

This is analogous to multi cores, where the each lane represent a core and more cores permit parallel processing. If the main core is too constrained for its processing power, the other secondary cores can help to lighten the computing job of the main core. Additionally, these cores can be used for distinct jobs within one process by programmers, which can permit more sophisticated optimizations.

32 bits and 64 bits architecture

A 2-tonne trailer carries more material than a 1-tonne trailer. Another way to carry more material is with trailer count, as a 2-trailer road train carries more material than a single-trailer semi truck.

The thing is, if you keep your trailer size the same, the only way to increase space is by increasing trailer quantity. Naturally this is not ideal, as it decreases the efficiency and speed of processes, as well as making the process of loading and unloading more time consuming.

This is analogous to memory addressing. When smaller word sizes (the size of numbers that the architecture directly manipulates) were prominent, there had to be a second number used to point to different memory locations (like a second trailer), which on most machines was called a segment register. This made most operations slow. By increasing word size, this was no longer necessary.

On 32-bit machines, 4 billion memory locations can be directly manipulated, while 64-bit machines can manipulate 18 quintillion memory locations (4 billion memory locations for every one memory location on a 32-bit machine).

Cache

To increase the efficiency, the warehouse is fit with the loading bay where the most popular goods are loaded first while waiting for truck to came back from deliveries.

This is analogous to cache. Accessing RAM is often a (relatively) slow operation, so the larger the processor's cache, the less often a processor has to access RAM for the data it needs. There are typically around 3 levels of cache in most modern processors, and each level is much smaller but much faster than the previous level (mainly due to proximity).

The processor will search the lowest level of cache for the data it needs, and if that is not found, a “cache miss” has occurred. Then, the processor will search the next cache level for the necessary data, until it checks RAM. Once a “cache hit” occurs, or once the data is found in RAM, the lower levels caches are populated indiscriminately with that section of data, so each cache is like a small window into the most recently used region of data.