Microprocessor Design/Basic Theory
This basic theory of microchip briefly describes the microchip's architecture by using a "goods truck analogy".
We can imagine the whole microchip itself as a giant city. We also assume that the city itself imports the goodies from Input and also export the goodies to the Outputs. In between the city, there are many highways connecting to the parts between the cities to process. The trucks are carrying goods across and through the city.
The first limit is obviously the speed of the delivery trucks. If the trucks can deliver faster, it will also deliver a lot more goodies across the city such as 2.0 million tonnes of goods per year (think of this in terms of 2.0Ghz ) compared to 2.5 million tonnes of goods per year (again, think of this in terms of 2.5Ghz). This is analogous to the 2.5 Ghz CPU which can process more data than 2.0 Ghz CPU.
However, there is a limit to how fast a delivery truck can drive on the highway; if the driver goes too fast, he might lose some of his cargo unexpectedly, or he might even crash. So, the speed of a single delivery truck is limited by the safety of the road. (Think this terms as clocking speed)
There are ways to make the highway safer such as make all the turns wider, construct guardrails, make the asphalt smoother, ensures there are no debris on the road ,etc., and by doing so will safely increase the maximum speed of the delivery trucks.
New fabrication processes also let you fit more transistors in a given space, which in turns gives you the space needed to implement a lot of the complicated logical structures. Any contaminants that land on the wafer will damage the chips. This also explains why the clean room which is used to fabricate the CPU is very clean (have very low count of parts per million per cubic meters).
If there is one truck operating across the city, the pending deliveries need to wait for the truck to come back from its previous destination before the orders can proceed. Therefore, the more trucks there are in standby, the faster the delivery process and thus creating lesser waiting time.
This is analogous to pipelining where the different tasks a processor has to carry out are split into separate "jobs", and when an instruction moves from one piece of the pipeline to the next, a new instruction can be started before the first instruction is totally finished.
A four laned road can carry more capacity of trucks compared to a road with a single lane . If the one lane is busy, the other 3 lanes can share the traffic load simultaneously to prevent the traffic jam.
This is analogous to multi cores where the each lane represent a core and more cores lead to parallel processing. If the main core is too constrained for its processing power, the other secondary cores can help to lighten the computing job of the main cores.
32 bits and 64 bits architecture
A 2 tonne truck is able to carry more load than a 1 tonne truck.
This is analogous to 64 bits architectures that are able to provide more memory space to the processor compared to 32 bits architectures. (4GB of memory) compared to 64 bits (4PB, 4 million GB).
To increase the efficiency, the warehouse is fit with the loading bay where the most popular goods are loaded first while waiting for truck to came back from deliveries.
This is analogous to *cache*. Accessing RAM is often a (relatively) slow operation, so the larger the processor's cache, the less often a processor has to access RAM for the data it needs. There are actually 3 levels of cache in most modern processors, and each level is much smaller but much faster than the previous level.