Fundamental Digital Electronics/Digital Adder
Contents
Half adder[edit]
When adding 2 numbers we will have a Sum and a Carry . Let first number be A and Second number be B then adding A + B will produce a Sum S and a carry C

0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1
From above, In term of logic gate AND will produce a sum of two input . logic gate XOR produce carry
Half Adder can constructed from AND gate and XOR gate as shown below
Full adder[edit]
The above case is just a special case when there is no Carry . If there is Carry then

Input Output 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1
A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting C_{i} to the other input and OR the two carry outputs. Equivalently, S could be made the threebit XOR of A, B, and C_{i}, and C_{o} could be made the threebit majority function of A, B, and C_{i}.
Multiplebit adders[edit]
Ripple carry adder[edit]
It is possible to create a logical circuit using multiple full adders to add Nbit numbers. Each full adder inputs a C_{in}, which is the C_{out} of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.
The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32bit [ripple carry] adder, there 32 full adders,so the critical path (worst case) delay is gate delays.
Carry lookahead adders[edit]
To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry lookahead adders. They work by creating two signals (P and G) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a '1'), a carry is generated in that bit position (both inputs are '1'), or if a carry is killed in that bit position (both inputs are '0'). In most cases, P is simply the sum output of a halfadder and G is the carry output of the same adder. After P and G are generated the carries for every bit position are created. Some advanced carry look ahead architectures are the Manchester carry chain, BrentKung adder, and the KoggeStone adder.
Some other multibit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time. These block based adders include the carry bypass adder which will determine P and G values for each block rather than each bit, and the carry select adder which pregenerates sum and carry values for either possible carry input to the block.
Other adder designs include the conditional sum adder, carry skip adder, and carry complete adder.
Lookahead Carry Unit[edit]
By combining multiple carry lookahead adders even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64bit adder that uses four 16bit CLAs with two levels of LCUs.