## Contents

When adding 2 numbers we will have a Sum and a Carry . Let first number be A and Second number be B then adding A + B will produce a Sum S and a carry C

$A$ $B$ $S$ $C$ 0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

From above, In term of logic gate AND will produce a sum of two input . logic gate XOR produce carry

$S=A\oplus B$ $C=A\cdot B$ Half Adder can constructed from AND gate and XOR gate as shown below The above case is just a special case when there is no Carry . If there is Carry then

Input Output
$A$ $B$ $C_{i}$ $C_{o}$ $S$ 0 0 0 0 0
0 1 0 0 1
1 0 0 0 1
1 1 0 1 0
0 0 1 0 1
0 1 1 1 0
1 0 1 1 0
1 1 1 1 1
$S=(A\oplus B)\oplus C_{in}$ $C_{out}=(A\cdot B)+(C_{in}\cdot (A\oplus B))$ A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the two carry outputs. Equivalently, S could be made the three-bit XOR of A, B, and Ci, and Co could be made the three-bit majority function of A, B, and Ci.  It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is a ripple carry adder, since each carry bit "ripples" to the next full adder. Note that the first (and only the first) full adder may be replaced by a half adder.

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit [ripple carry] adder, there 32 full adders,so the critical path (worst case) delay is $32*3=96$ gate delays.