Embedded Systems/Cypress PSoC Microcontroller/Application Notes
The Cypress application notes are a good start, but they often do not have all the information required, have bugs, are out of date for more recent microcontrollers or are otherwise inadequate. This is meant to be a fix to //add to// the existing documentation, not a wholesale copy-and-paste of the existing application notes.
- Embedded Systems/Cypress PSoC Microcontroller/Application Notes/AN2100 - A Serial Bootloader
- Implementing FFT Algorithms on PSoC(R) System - AN42877 : (where is the code?) ... also see Embedded Systems/Floating Point Unit#FFT
First you must read the Data sheet then you have to coment on the product many engineers had been worked, and even though if they want to release the product they will be checking 1000 times in 1000 ways please think and command to anyone Thanx and Regrads
MANJUNATH D L email@example.com
Q: These PSoC chips can be set up to do 14 bit ADCs and 9 bit DACs. But what is the (maximum) sampling frequency at 14 bits and 2 analog inputs? What is the maximum sampling frequency if I'm happy with only 12 or 8 bits of resolution?
If I feed the signal to the on-chip PGA, crank its gain all the way up, and feed the PGA output to a ADC ... will I get 10 real bits of signal data, or am I getting nothing but noise?
A: See Analog - ADC Selection - AN2239 by Dennis Seguine. It discusses the trade off between sampling rate and resolution. It specifically mentions "DELSIG8 ... output rate of 31 ksps ... (when) column clock equal to 2.0 MHz" and "DELSIG11 ... output rate of 7.8 ksps ... (when) column clock equal to 2.0 MHz".
You may also find these app notes useful: