Digital Electronics/Synchronous Device/Register
Register is a Digital Device constructed from basic Digital Gates to perform a task or a function
In some situations it may be desirable to dictate when the latch can and cannot latch. The gated SR latch is a simple extension of the SR latch which provides an Enable line which must be driven high before data can be latched. Even though a control line is now required, the SR latch is not synchronous, because the inputs can change the output even in the middle of an enable pulse.
When the Enable input is low, then the outputs from the AND gates must also be low, thus the Q and Q outputs remain latched to the previous data. Only when the enable input is high can the state of the latch change, as shown in the truth table. When the enable line is asserted, a gated SR latch is identical in operation to an SR latch.
The Enable line is sometimes a clock signal, but is usually a read or write strobe.
Enable S R Q Q 0 0 0 Latch 0 0 1 Latch 0 1 0 Latch 0 1 1 Latch 1 0 0 Latch 1 0 1 0 1 1 1 0 1 0 1 1 1 Metastable
The D latch (D for "data") or transparent latch is a simple extension of the gated SR latch that removes the possibility of invalid input states.
Since the gated SR latch allows us to latch the output without using the S or R inputs, we can remove one of the inputs by driving both the Set and Reset inputs with a complementary driver: we remove one input and automatically make it the inverse of the remaining input.
The D latch outputs the D input whenever the Enable line is high, otherwise the output is whatever the D input was when the Enable input was last high. This is why it is also known as a transparent latch - when Enable is asserted, the latch is said to be "transparent" - it signals propagate directly through it as if it isn't there.
Enable D Q Q 0 0 Latch 0 1 Latch 1 0 0 1 1 1 1 0
D latches are often used in I/O ports of integrated circuits and are available as discrete devices, often multiply packaged. An example is the 74HC75, part of the 7400 series of ICs, containing four separate D latches.
A T flip-flop is a device which swaps or "toggles" state every time it is triggered if the T input is asserted, otherwise it holds the current output. This behavior is described by the characteristic equation:
and can be described either of the following tables:
When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This 'divide-by' feature has application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or D flip-flop (T input and Qprev are connected to the D input through an XOR gate).
The JK flip-flop is a simple enhancement of the SR flip-flop where the state J=K=1 is not forbidden. It works just like a SR FF where J is serving as set input and K serving as reset. The only difference is that for the formerly “forbidden” combination J=K=1 this flip-flop now performs an action: it inverts its state. As the behavior of the JK flip-flop is completely predictable under all conditions, this is the preferred type of flip-flop for most logic circuit designs. But there is still a problem i.e. both the outputs are same when one tests the circuit practically. This is because of the internal toggling on every propagation elapse completion. The main remedy is going for master-slave jk flip-flop, this ff overrides the self(internal) recurring toggling through the pulsed clocking feature incorporated.