Digital Electronics/Logic NAND

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Logic NAND[edit | edit source]

NAND gates are one of the two basic logic gates (the other being NOR gates) from which any other logic gates can be built. Due to this property, NAND and NOR gates are sometimes called "universal gates". However, modern integrated circuits are not constructed exclusively from a single type of gate. Instead, EDA tools are used to convert the description of a logical circuit to a netlist of complex gates (standard cells) or transistors (full custom approach).

Combinational Gates[edit | edit source]

NOT[edit | edit source]

A NOT gate is made by joining the inputs of a NAND gate. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT part.

Desired Gate NAND Construction
Truth Table
Input A Output Q
0 1
1 0

AND[edit | edit source]

An AND gate is made by following a NAND gate with a NOT gate as shown below. This gives a NOT NAND, i.e. AND.

Desired Gate NAND Construction
Truth Table
Input A Input B Output Q
0 0 0
0 1 0
1 0 0
1 1 1

OR[edit | edit source]

If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. However to be an OR gate, if any input is 1, the output must also be 1. Therefore, if the inputs are inverted, any high input will trigger a high output.

Desired Gate NAND Construction
Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 1

NOR[edit | edit source]

A NOR gate is simply an OR gate with an inverted output:

Desired Gate NAND Construction
Truth Table
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 0

XOR[edit | edit source]

An XOR gate is made by connecting four NAND gates as shown below. This effectively represents the formula: (A NAND (A NAND B)) NAND (B NAND (A NAND B)).

Desired Gate NAND Construction
Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 0

XNOR[edit | edit source]

An XNOR gate is constructed using five NAND gates. Three of the gates are connected in an OR topology. A logical expression for this arrangement is ((A OR B) NAND (A NAND B)).

Desired Gate NAND Construction
Truth Table
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 1

External links[edit | edit source]


Reference[edit | edit source]

  • Floyd, Thomas, L. (1997), Digital Fundamentals (6th ed.), Englewood Cliffs, NJ: Prentice-Hall, ISBN 0133984885.