Circuit Idea/Revealing the Truth about ECL Circuits
Circuit idea: Use a transistor stage with switchable voltage and current emitter sources: at low input voltage, disconnect the sources from the emitter; during the transition, connect both the voltage and current source; at high input voltage, connect only the current source to the emitter.
Revealing the basic idea[edit | edit source]
ECL gates are maybe the oddest logic circuits that arouse many questions. For example, in contrast to other logic gates, they are based on a differential amplifier... but why? What problem does it solve in these circuits? They say the differential amplifier acts here as a current steering switch. Well, it steers... but we want to know why the emitter current is steered between the two legs; with what purpose the current is steered. To answer these questions, we have first to show what the fundamental problem of ordinary logic circuits is and then to show how this problem is solved in ECL.
The fundamental idea behind ECL is not differential amplifier or current steering although, in the middle of transition, the circuit is exactly a differential amplifier (an emitter-coupled amplifier) that steers the current between the legs. Differential amplifier, emitter-coupled amplifier and current steering are misleading concepts in explaining ECL circuits. They cannot explain what fundamental problem ECL has solved as they focus our attention to the middle part of the transition where actually there is no any problem! In this area, the transistors of all the ordinary logic circuits (RTL, DCTL, DTL and TTL) work perfect as common-emitter stages in active regime. If we were staying in this area, there was no any need to replace them with this more sophisticated and odd 3-component structure figuratively named long-tailed pair as it would do the same - it would work as the same common-emitter stage!
The problem of saturation[edit | edit source]
A problem appears when the input voltage approaches the high threshold (logical "1") and the transistors of the ordinary logic circuits (RTL, DCTL, DTL and TTL) saturate; as a result, they work slowly. But, as curious readers would think, the differential (emitter-coupled) amplifier couldn't solve this problem as, in this area, the reference transistor T3 is cut-off and the differential amplifier is not an amplifier. In actul fact, the long-tailed pair is cut in two and this structure is no more a differential amplifier; its two new parts are something else. So, the paradox of this classic viewpoint is that we use a differential amplifier where actually it is not a differential amplifier!
Saturation is the fundamental problem that ECL circuits solve at high input voltage (logical "1"). This and only this is the amazing feature of ECL; the other advantages (as the presence of two inverse outputs) are inessential. So, it is our primary duty to show in this page the basic idea (the clever trick, the circuit solution, the remedy...) that is used to prevent saturation. But how can we prevent saturation? Let's see and compare various anti-saturation techniques.
How to prevent saturation[edit | edit source]
We can drive the transistor from the side of the base and from the side of the emitter. So, we may prevent saturation indirectly from the side of the base by limiting the base current or directly from the side of the emitter by limiting the very collector current.
...from the side of the base...[edit | edit source]
We have two techniques for limiting the base current that require the presence of a base resistor (i.e., they are inappropriate for direct-coupled circuits).
- The simplest and obvious solution is to decrease the base current by increasing the base resistance. But the large tolerances of β make this approach unrealizable  as the collector current and the point of saturation will depend on the particular transistor.
- Another but reliable and wide used β-independent technique for preventing saturation is to detract the excessive base current by a diode negative feedback (connecting a Schottky diode between the collector and the base). Until the transistor is in active mode, the diode is cut-off and does not affect the base current. When it approaches the saturation point, the diode turns on and deprives the excessive base current.
...from the side of the emitter.[edit | edit source]
Finally, we may try to avoid saturation by limiting the very collector (emitter) current and thus we will finally arrive at ECL. But we cannot set the desired emitter current in a common-emitter stage (DCTL) simply by inserting a constant current source (or, in the simpler case, an ohmic resistor) between the emitter and ground as we will not be able to control at all (or slightly, in the case of the resistor) the collector current from the base. Why? The answer is that the current source (the emitter resistor) will introduce series negative feedback and the common-emitter amplifying stage will transmute into a stage with emitter degeneration. As a result, when we change the input base voltage to change the collector current, the transistor changes in the same manner its emitter voltage and we do... nothing:( Figuratively speaking, when we "move" the base voltage, the transistor "moves" in the same manner its emitter voltage (it operates as an emitter follower). The emitter voltage has become "soft", "pliable", "movable"...; but to control the collector current the emitter voltage has to be "hard", steady, fixed...
This is a fundamental problem of analog circuit design - how to set the desired collector current (the quiescent point) from the emitter without losing control from the base. Or, in other words, how to make the emitter voltage "soft" for the undesired influences and "hard" for the useful input voltage applied to the base. Typical examples: an AC amplifier with emitter degeneration suppresses the slow DC variations and amplifies rapidly changing AC input variations; a differential transistor amplifier suppresses common-mode signals and amplifies differential input signals; finally, an ECL gate suppresses the input voltage variations near to the high threshold (input logical "1") and amplifies them significantly during the transition. It is clear that there is some common powerful idea in these apparently different circuits... What is it?
Arriving at powerful ECL idea[edit | edit source]
Obviously, to make the emitter voltage "soft", we have to insert a constant current source (actully, a current-stable element) and v.v., to make the emitter voltage "hard", we have to insert a constant voltage source (a voltage-stable element). Instead to replace the current source with a voltage source we may just connect the voltage source in parallel to the current source as it will define the voltage across the combination of two elements. In the first two examples above, the voltage sources are permanently connected to the current ones but they appear only at useful input signals. In the AC amplifier, the bypass emitter capacitor follows the slow DC variations and does not affect the current source; but it begins acting as a constant voltage source at rapidly changing AC input variations. In the differential amplifier, the right emitter voltage follows the left one at common-mode and does not affect the current source; but it becomes steady (or opposite changing) at single-ended (or differential) mode. In ECL gate, solely the constant current source is connected in the emitter when the input voltage is near to the high threshold (input logical "1"); both the constant current source and the constant voltage source are connected in the emitter during the transition (the sources are commutated by the transistor's base-emitter "diode switches" S1 and S2 on the picture). Let's consider the three possible configurations that we may observe in ECL operation at the possible input voltages.
- VIN < VL, VIN = VL (logical "0"). T1 is cut off; VY = 0 V and does not depend on VIN. Both the current source (RE) and the voltage source (T3) are disconnected from the input part (but they are connected to each other).
- VL < VIN < VH (transition). T1 operates in active regime (common-emitter configuration) with both the parallel connected current source (RE) and voltage source (T3) inserted in its emitter. There is no negative feedback. VY depends significantly on VIN since the voltage source dominates over the current one and fixes T1's emitter voltage (it is "hard").
- VIN = VH, VIN > VH (logical "1"). T3 is cut off and there is no voltage source. Only the current source (RE) is connected in T1's emitter (emitter degeneration). There is a series negative feeddback. VY = VL and the collector current does not depend at all (in the case of constant current source) or depends slightly (in the case of emitter resistor) on VIN since T1's emitter voltage is "soft".
Finally, let's say the basic idea behind ECL with one sentence:
ECL is based on a transistor stage with switchable voltage and current emitter sources: at low input voltage, the sources are disconnected from the emitter; during the transition, both the voltage and current source are connected; at high input voltage, only the current source is connected to the emitter.
How the powerful ECL idea is implemented[edit | edit source]
The powerful ECL idea above may be realized by an emitter-coupled ("long-tailed") pair. Look at the picture that represents a generalized circuit diagram of a typical ECL circuit. It differs slightly from the particular MECL 10k (the additional reference emitter follower Q4 is omitted and additional resistors are connected in the emitters of the output transistors). The left part consists of two parallel-connected input transistors T1 and T2 (an exemplary two-input gate is considered) implementing NOR logic. The base voltage of the right transistor T3 is held fixed by a reference voltage source - the voltage divider with a diode thermal compensation (R1, R2, D1 and D2); thus the emitter voltages are kept relatively steady. As a result, the common emitter resistor acts nearly as a current source. The output voltages at the collector load resistors RC1 and RC3 are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5. The output emitter resistors RE4 and RE5 do not exist in all versions of ECL.
Scrutinizing the ECL operation[edit | edit source]
Let's assume we investigate an ECL inverter: the input voltage is applied to T1's base and T2's input is unused (T2 does not exist). Assume also the circuit has low voltage threshold VL = -1.7 V and high voltage threshold VH = -0.9 V that are situated symmetrically (±0.4 V) with respect to the reference voltage VREF = -1.3 V.
Let's arrange uniformly the circuit components on the circuit diagram above and stretch it so that it to fill out the drawing. Then, to visualize the invisible electrical attributes, let's overlay a picture of voltage and current relief. In this attractive presentation, voltages and voltage drops are represented by red colored bars, whose heights are proportional to the corresponding voltage magnitudes (an association with a water column); currents are represented by green colored loops with corresponding topology and thickness that is proportional to the magnitude of the current (an association with a water flow). Having a look at this picture, you can instantly get a notion of how "high" voltages (drops) are and how they are related; you can see how big currents are and how they flow.
Below the low voltage threshold[edit | edit source]
Actually, this situation will never occur if the circuit is driven by another identical ECL circuit; it will occur only if the circuit is driven by an input voltage source with lower voltage than the low voltage threshold. But let's consider it; it is still interesting.
Imagine the input voltage has got down vastly below the low voltage threshold VL (e.g., we have connected T1 base to VEE = -5.2 V). At this stage, think of the voltage divider R1-R2 and the emitter follower T3 as of a voltage source (voltage stabilizer) that fixes T1 emitter voltage at VE = VB3 - VBE3 = -1.3 - 0.7 = -2 V. As a result, T1 base-emitter junction becomes backward biased (VBE1 = VEE - VE = -5.2 + 2 = -3.2 V); T1 is cut off and its collector voltage is almost 0 V. If we continue decreasing the input voltage, at given point a zener breakdown will occur. T1 will begin "pulling-down" T3 emitter voltage (a common-base configuration). As a result, T3 collector current/voltage will begin increasing/decreasing rapidly.
In this state, the circuit does not consume a current from the previous stage since T1 base-emitter voltage is less than the cut-in voltage or T1 base-emitter junction is backward biased. So, the input resistance is extremely high.
Low input voltage (logical "0")[edit | edit source]
Left part. Now imagine our circuit is driven by another identical ECL circuit whose output stage (the emitter follower T5') has placed low input voltage VL = -1.7 V at T1 base. Its base-emitter voltage is VBE1 = VL - VE = -1.7 + 2 = 0.3 V; T1 is cut off and its collector voltage is almost 0 V. The T4 base current flows through RC1 and creates only a small voltage drop about VRc1 = 0.2 V. So, the output voltage VY = 0 - VRc1 - VBE4 = -0.2 - 0.7 = -0.9 V (logical 1") and does not depend on the gate input voltage. The left part of the long-tailed pair is disconnected from the right part and does not affect it.
In this state, the circuit does not consume a current from the previous stage since T1 base-emitter voltage is less than the cut-in voltage. So, the input resistance is high.
Right part. Now, think of the voltage divider R1-R2, the emitter follower T3 and the emitter resistor RE as a current source passing a current IC3 = (VR2 + 2VF - VBE3)/RE through the T3 collector resistor RC3 (this current will determine the maximum T1 collector current in the next state when it will be steered to flow through T1; so, it has to be lower than T1 saturation current to prevent saturation). Or, if you prefer, think of the combination RE, T3 and RC3 as of a common-emitter amplifier (actually, it is not an amplifier but an attenuator with K = Rc3/Re < 1) with emitter degeneration driven by the constant voltage VREF = VR2 + 2VF. The resistance RC3 (245 Ω) is chosen so that, at the reference input voltage VB3 = -1.3 V, the T3 collector current to create voltage drop VRc3 = 1 V across it. So, the output voltage VY = 0 - VRc3 - VBE5 = 0 - 1 - 0.7 = -1.7 V (logical "0"). The voltage drop across T3 (VCE3 = VC3 - VE = -1 + 2 = 1 V) is high enough to keep T3 in the active region. The output voltage depends on the resistances RE, RC3, R1 and R2 and will vary if they vary. But these variations will not accumulate after next several stages since the input transistor T1 (T2) of the next ECL gate will be cut off and its collector voltage (accordingly, the output voltage VY) will not depend on the gate input voltage. T3 collector voltage (accordingly, the output voltage VY) of the next gate will not depend on the gate input voltage as well; it will depend on its reference voltage.
Low-to-high transition[edit | edit source]
Now imagine the input voltage begins rising over the low threshold VL = -1.7 V. T1 begins opening; it increases its emitter current and voltage drop across RE. Figuratively speaking, T1 begins "pulling up" T3 emitter:) thus closing gradually T3 and taking bit by bit its current. The situation is very interesting and it is worth to be generalized as other legendary circuits (e.g., common-base amplifying stage) are based on the same idea.
During the transition, two voltage sources (more precisely, two voltage-stable elements) are connected in parallel (T1 emitter follower from the left side and T3 emitter follower from the right side) and are supplied by a common current source (the emitter resistor RE supplied by VEE). Figuratively speaking, the two voltage sources are in conflict:) as the right voltage source does its best to keep a steady emitter voltage while the left voltage source tries to increase it. Note these voltage sources are negative feedback systems that react to any intervention applied to their outputs. So, when T1 begins opening to increase its emitter current and emitter voltage, as an answer, T3 begins closing to lower its emitter current and accordingly to decrease the emitter voltage. As a result, the collector current redirects (fades) rapidly from the right to the left side at approximately constant emitter voltage.
During the middle of transition the input resistance is low since the circuit behaves as a common-emitter stage with relatively steady emitter voltage. There is no (it is slight enough) negative feedback in the input stage since there is a small emitter resistance.
Now look at the picture above to see how the two collector currents were changing during the transition. At the middle area, the two currents change (fade) rapidly. Approaching the high threshold VH = -0.9 V, T3 collector current becomes almost zero while T1 collector current begins changing slowly. How do we explain this behavior? Let's try answering this question.
During the transition, the right (reference) emitter follower T3 is connected to T1 emitter and fixes its voltage (makes it "stiff", "hard", stable...) Figuratively speaking, the reference emitter follower T3 shorts the emitter resistance during the transition. So, there is no negative feedback in the input stage and it acts almost as a CE amplifier with high gain (transconductance G). At the end of the transition, the reference emitter follower T3 "unhooks" from T1 emitter; the emitter resistor "appears" and introduces a series negative feedback (the so-called emitter degeneration). The input stage already acts as a real CC amplifier (emitter follower) with "soft" emitter voltage that follows the input one. As a result, the T1 collector current becomes IC1 = IRE = (VRE5' - VBE1)/RE and its curve begins loosing its nerve:) Accordingly, VC1 and VY continues changing slowly (Y's logical "0" depends slightly on the input voltage). Note there is no such a problem with T3 collector current in the beginning of transition as it is set by the steady reference voltage (Y's logical "0" does not depend on the input voltage).
If we are curious and penetrative enough, we may see the same trick (connecting in parallel two voltage-stable elements with different thresholds to redirect the current to the element with the lower threshold) in many other circuits. For example, when we ground a TTL (or DTL) input, we connect one base-emitter junction (of the multiple-emitter transistor) in parallel to two series-connected junctions (the base-collector junction of the multiple-emitter transistor and the base-emitter junction of the second transistor); as a result, the input single junction sinks all the base current. The same trick is applied in the TTL totem-pole output stage where, at output logical "0", the transistor V2 connects the V4 base-emitter junction in parallel to the series-connected V3 base-emitter junction and deliberately inserted V5 junction; as a result, the single V4 base-emitter junction deprives all the V3 base current. This trick can be easily demonstrated by connecting in parallel different LEDs as they show where current flows and how big they are without connecting an ammeter. Imagine we have handful of different colored LEDs. Let's connect consecutively a 2 V red LED to the same 2 V red (green, yellow) LED, then to a 3 V blue LED and finally, to a composed 4 V "LED" (two connected in series 2 V red LEDs). We will be deeply impressed when see how the single red LED extinguishes LEDs or combination of LEDs having higher forward voltage.
High input voltage (logical "1")[edit | edit source]
At the end of the transition, when the input voltage reaches the high threshold VH = -0.7 V, all the T3 collector current is taken by T1. This is its maximum collector current that is lower than its saturation current ISAT = VEE/(RC1 + RE) and T1 is prevented against saturation. Note the final collector current does not depend on T1's β (on particualar transistor). It depends only on VEE, RE and RC1 and this is the benefit of using the powerful current steering idea here!
Left part. The preceding output stage (the emitter follower T5') has already set high input voltage VH = -0.9 V at T1 base. As above, you may think of the emitter follower T1 and the emitter resistor RE as a voltage-controlled current source (voltage-to-current converter or a transconductance amplifier) passing a current IC1 = (VRE5' - VBE1)/RE through the collector resistor RC1. Or you may think again of the combination RE, T1 and RC1 as of a common-emitter amplifier (as above, it is sooner an attenuator with K = Rc1/Re < 1) with emitter degeneration driven by the constant voltage VRE5'. The resistance RC1 (220 Ω) is chosen so that, at high input voltage VIN = VH = -0.9 V, the T1 collector current to create voltage drop VRc1 = 1 V across it. So, the output voltage VY = 0 - VRc1 - VBE4 = 0 - 1 - 0.7 = -1.7 V (logical "0"). The voltage drop across T1 is VCE1 = VC1 - VE = - 1 + 1.6 = 0.6 V and the transistor is still not saturated. The output voltage depends on the resistances RE, RC1 and the input voltage VIN; so, it will vary if they vary. As Rc1/Re = 0.22 the output voltage depends slightly on the input voltage (it won't depend at all if we replace RE by a constant current source). But again, as above, these variations will not accumulate after next several stages since the input transistor T1 (T2) of the next ECL gate will be cut off and its collector voltage (accordingly, the output voltage VY) will not depend on the gate input voltage. T3 collector voltage (accordingly, the output voltage VY) of the next gate will not depend on the gate input voltage as well; it will depend on its reference voltage.
At this stage, the input resistance becomes very high since the circuit begins acting as emitter follower (common-collector stage).
Right part. At this point, the input emitter follower T1 has "pulled-up" the T3 emitter to a level of VE = -1.6 V. As a result, the base-emitter voltage of T3 is VBE3 = VB3 - VE = -1.3 + 1.6 = 0.3 V; so, T3 is cut off and its collector voltage is almost 0 V. Only the T5 base current flows through RC3 and creates small voltage drop about VRc3 = 0.2 V. So, the output voltage VY = 0 - VRc3 - VBE5 = -0.2 - 0.7 = -0.9 V (logical 1") and does not depend on the gate input voltage. The right part of the long-tailed pair is disconnected from the left part and does not affect it.
Above the high voltage threshold[edit | edit source]
Actully, this situation will never occur if the circuit is driven by the same ECL circuit; it will occur only if the circuit is driven by an input voltage source with higher voltage than the high voltage threshold. But let's consider it; it is still interesting.
If we continue increasing the input voltage above this level (e.g., if we connect T1 base to ground or to a positive voltage source), T1 will saturate presently. The collector and emitter points join and the input voltage transfers directly through the forward-biased T1 base-emitter and base-collector junctions to this point; accordinghly, VY follows VIN's variations and the current through RC1 begins decreasing. The input part behaves as a voltage divider affected in its output; so, the input resistance becomes relatively low again (RIN = Rc1||Re).
Nevertheless, T1 continues "moving up" T3 emitter. After the point where VIN = -0.6 V, T3 base-emitter junction becomes backward biased and, at given point, a zener breakdown occurs.