A-level Computing 2009/OCR AS text book/1.1.1 Structure and function of the processor

The specification highlights the following topics which must be covered.

a) The Arithmetic and Logic Unit; ALU, Control Unit and Registers (Program Counter; PC, Accumulator; ACC, Memory Address Register; MAR, Memory Data Register; MDR, Current Instruction Register; CIR). Buses: data, address and control: How this relates to assembly language programs.
b) The Fetch-Decode-Execute Cycle, including its effect on registers. c) The factors affecting the performance of the CPU: clock speed, number of cores, cache.
d) The use of pipelining in a processor to improve efficiency.
e) Von Neumann, Harvard and contemporary processor architecture.

C The factors effecting performance of the CPU

Clock speed is the number of instructions which can be completed in one second, recently this has been measured in Ghz (1 Billion instructions per second). Revise Mhz, Khz, Thz as well to get a better idea of how CPUs have developed over the last three decades and how modern CPus compare to each other.

Number of Cores, as it has become harder to fit more switches on to a chip it has become common practice to combine multiple CPUs onto one chip and have them work in parallel. However having two 2.2Ghz cores would lead to double the performance. The additional cores speeds are limited by algorithms which run the fetch execute and decode process. In addition to this few programs are created developed to be run on a parallel core system, so benefits are limited to running different programs are limited.

The factor	Increase in capacity or number	Decrease in capacity or number
Clock Speed	This will increase the speed of the CPU, as more instructions can be completed per second	This will decrease the speed of the CPU, as less instructions can be completed per second
Number of cores	As the number of cores increase (2,4,6,8...) speed increase but it is not exactly proportional so does not double every time	As the number of cores decrease the speed of the CPU decreases as less instructions can be completed in parallel.
Cache		Example