With the exception of the 16-bit status register, all 68000 registers are 32-bits wide.
There are eight data registers: d0, d1, d2, d3, d4, d5, d6, and d7. These are intended to hold numbers that will have various mathematical and logical operations performed on them.
There are seven address registers: a0, a1, a2, a3, a4, a5, and a6. These are typically used as pointers.
There is one active stack pointer: SP, also called a7. Normally the processor is in user mode. In user mode, SP refers to the User Stack Pointer (USP) register. (During interrupts, the active stack pointer SP is another register called the Interrupt Stack Pointer or the System Stack Pointer. The 68020 and higher processors have a third register called the Master Stack Pointer. Neither the ISP nor the MSP can be accessed in user mode).
The 68K includes special addressing modes that make it easy to manipulate a data stack structure using any address register.
The Program Counter (PC) points to the current instruction. On the 68000, only the lower 24 bits output to any pins, giving a maximum addressing range of 16MiB. The Program Counter is changed automatically when a new instruction is loaded or when a BRA, Bcc, BSR, JMP, JSR, RTS, or RTE instruction is used. It can also be used as a pointer in PC relative addressing modes.
The Condition Code Register (CCR) consists of the lower byte of the Status Register (SR). Only the lower byte is accessible in user mode, and of this, only the first five bits are useful. In supervisor mode, the entire 16-bit register is accessible. The register looks like this:
Here's the decoded register contents:
|I0||Interrupt priority mask bit 1|
|I1||Interrupt priority mask bit 2|
|I2||Interrupt priority mask bit 3|
|M||Master/Interrupt switch. Determines which stack mode to use if S is set. If M is clear, SP refers to ISP, else SP refers to MSP. This bit is always clear on processor models lower than 68020.|
|S||Supervisor Mode flag. If clear, SP refers to USP. If set, look at M to determine what stack SP points to.|
|T0||Trace bit 1. If set, trace on change of program flow. This bit is always cleared on processor models lower than 68020.|
|T1||Trace bit 2. If set, trace is allowed on any instruction. DO NOT SET BOTH TRACE BITS AT THE SAME TIME!|