User:BORGATO Pierandrea/Collections/Clock & Data recovery

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Clock & Data recovery[edit]

The CDR function is a simple one and just three architectures are sufficient to model it. The actual implementation of the CDR may differ from the neat, simple analog structure of the mathematical models. Complex digital blocks, DLLs, DSPs may disguise the architecture, but the fundamental operation of the CDR will not differ. Knowledge of the three models is fundamental to imagine, specify, design, check, measure and interpret the behavior of the CDR. Reference to them is the best way to avoid confusion and errors.[edit]

Definition of (phase) jitter
Jitter is far from sinusoidal..
Models can only be linear..
Acquisition, tracking and jitter performances
Networks and clocks
Buffer Memory (Elastic Buffer)
Clock domains
Cascades of Buffers and CDRs, delays and tolerance
Burst and Continuous transmission modes
CDR basic blocks
The CDR' amplifier/filter
The CDR phase comparator
The CDR Phase and Frequency Detector PFD
CDR structures
Structures and types of CDRs
Examples of structures
The jitter tolerance function
The noise spectrum is shaped by the PLL structure
1st order (type 1) loop
The CDR based on a first order PLL
Applications of the 1st order type 1 architecture
2nd order loops of type 1 and 2
The (slave) CDR based on a second order PLL
2nd order type 1
Applications of the 2nd order type 1 architecture
2nd order type 2
Applications of the 2nd order type 2 architecture
Miscellanea and conclusion