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File:Verilog Bus.svg

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Original file ‎(SVG file, nominally 125 × 125 pixels, file size: 13 KB)

Description
English: A diagram of a bus, made up of 6 wires, a[0] to a[5]. The bus is then a[5:0], and has width 6.
Date
Source Own work
Author Inductiveload
Permission
(Reusing this file)
Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
In some countries this may not be legally possible; if so:
I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

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inception

23 May 2009

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Date/TimeThumbnailDimensionsUserComment
current13:01, 23 May 2009Thumbnail for version as of 13:01, 23 May 2009125 × 125 (13 KB)Inductiveload{{Information |Description={{en|1=A diagram of a bus, made up of 6 wires, a[0] to a[5]. The bus is then a[5:0], and has width 6.}} |Source=Own work by uploader |Author=Inductiveload |Date=2009/05/23 |Permission={{PD-self}} |other_ve

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