VHDL for FPGA Design/D Flip Flop

 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity D_FF_VHDL is
   Port(D: in std_logic;
 	Reset: in std_logic;
 	Clock_enable: in std_logic;
        Clock: in std_logic;
        Output: out std_logic);
end D_FF_VHDL;
 
architecture Behavioral of D_FF_VHDL is
begin
   process (Clock)
   begin
      if Clock'event and Clock='1' then  
         if Reset='1' then   
            Output <= '0';
         elsif Clock_enable ='1' then
            Output <= D;
         end if;
      end if;
   end process;
end Behavioral;