VHDL for FPGA Design/4-Bit Shift Register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity Shift_register_VHDL is
 
   port( Clock: in std_logic;
 	 L,w: in std_logic;
 	 Output: out std_logic_vector(3 downto 0);
 	 Input: in std_logic_vector( 3 downto 0));
 
end Shift_register_VHDL;
 
architecture Behavioral of Shift_register_VHDL is
   signal temp: std_logic_vector(3 downto 0);
begin
   process
   begin
      wait until Clock'event and Clock='1';
 	 if L='1' then
 	    temp <= Input;
 	 else 
 	    for i in 0 to 2 loop
 	       temp(i) <= temp(i+1);
 	    end loop;
 	    temp(3) <= w;
 	 end if;
    end process;
    Output <= temp;
end Behavioral;