VHDL for FPGA Design/4-Bit Johnson Counter with Reset

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Counter johnson fi.png

Johnson Counter[edit]

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
 
entity Johnson is
   port ( CLK : in    std_logic; 
          CLR : in    std_logic; 
          A   : out   std_logic; 
          B   : out   std_logic; 
          C   : out   std_logic; 
          D   : out   std_logic);
end Johnson;
 
architecture BEHAVIORAL of Johnson is
   attribute INIT       : string ;
   attribute BOX_TYPE   : string ;
   signal XLXN_44 : std_logic;
   signal A_DUMMY : std_logic;
   signal B_DUMMY : std_logic;
   signal C_DUMMY : std_logic;
   signal D_DUMMY : std_logic;
   component FDC
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C   : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute INIT of FDC : component is "0";
   attribute BOX_TYPE of FDC : component is "BLACK_BOX";
 
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
 
begin
   A <= A_DUMMY;
   B <= B_DUMMY;
   C <= C_DUMMY;
   D <= D_DUMMY;
   XLXI_20 : FDC
      port map (C=>CLK,
                CLR=>CLR,
                D=>XLXN_44,
                Q=>A_DUMMY);
 
   XLXI_21 : FDC
      port map (C=>CLK,
                CLR=>CLR,
                D=>A_DUMMY,
                Q=>B_DUMMY);
 
   XLXI_22 : FDC
      port map (C=>CLK,
                CLR=>CLR,
                D=>B_DUMMY,
                Q=>C_DUMMY);
 
   XLXI_23 : FDC
      port map (C=>CLK,
                CLR=>CLR,
                D=>C_DUMMY,
                Q=>D_DUMMY);
 
   XLXI_25 : INV
      port map (I=>D_DUMMY,
                O=>XLXN_44);
 
end BEHAVIORAL;

Simulation Waveform[edit]

Johnson fi.png