Embedded Systems/ARM Assembly Language

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ARM Instruction Set Format
Instruction 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADC Cond 0 0 I 0 1 0 1 S Rn Rd shifter operand
ADD Cond 0 0 I 0 1 0 0 S Rn Rd shifter operand
AND Cond 0 0 I 0 0 0 0 S Rn Rd shifter operand
B, BL Cond 1 0 1 L signed_immed_24
BIC Cond 0 0 I 1 1 1 0 S Rn Rd shifter operand
BKPT 1 1 1 0 0 0 0 1 0 0 1 0 immed 0 1 1 1 immed
BLX (1) 1 1 1 1 1 0 1 H signed_immed_24
BLX (2) Cond 0 0 0 1 0 0 1 0 SBO SBO SBO 0 0 1 1 Rm
BX Cond 0 0 0 1 0 0 1 0 SBO SBO SBO 0 0 0 1 Rm
CDP Cond 1 1 1 0 opcode_1 CRn CRd cp_num opcode_2 0 CRm
CLZ Cond 0 0 0 1 0 1 1 0 SBO Rd SBO 0 0 0 1 Rm
CMN Cond 0 0 I 1 0 1 1 S Rn SBZ shifter operand
CMP Cond 0 0 I 1 0 1 0 S Rn SBZ shifter operand
LDC Cond 1 1 0 P U N W 1 Rn CRd cp_num 8_bit_word_offset
LDM (1) Cond 1 0 0 P U 0 W 1 Rn register_list
LDM (2) Cond 1 0 0 P U 1 0 1 Rn 0 register_list
LDM (3) Cond 1 0 0 P U 1 W 1 Rn 1 register_list
LDR Cond 0 1 I P U 0 W 1 Rn Rd addr_mode