User:BORGATO Pierandrea
Contents
Application of the 21 architecture[edit]
This architecture is used in practice for:
 line regenerators, and for
 slave clocks in long distance (=Telecom) networks.
The implementation with linear phase comparator and linear VCO is the typical case, as it best fits those target applications.
This is the architecture that produces the sharpest high frequency rejection (40 dB/dec), that is important when:
 long distance links (=large distortions) affect the line signal with ISI and noise;
 regenerators are connected in series to cover a very long distance span.
The use of a linear comparator (in contrast to a possible bangbang alternative) generates very little noise.
As applications inside long distance equipment are less cost sensitive, the use of a linear comparator and of a linear VCOs with low noise and good linearity is possible.
 The application of all PLL elements within their linear range allows to match the tight, demanding specifications that are typical of the Telecom world.
The cascading of of several CDRs in a long distance connection becomes possible because of the low noise generation, good input noise rejection and predictable characteristics.

 The use of linear circuit blocks in these applications makes the linear model of the 21 architecture really and directly useful!
The ITUT Recommendations generally indicate as a reference model the model that corresponds to the 21 architecture.

 For instance:
 “a SEC will generally mimic the behavior of a 2nd order (type 1) linear analogue phase locked loop. This allows the use of the terms (equivalent) 3 dB bandwidth and (equivalent) damping factor, as they are used in analog PLL theory, irrespective of the fact that in the implementation of a SEC, digital and/or nonlinear techniques may be used."^{[1]}

 ( SEC: a SDH equipment slave clock)
In fact, when requirements are the following, like in a telecom networks:
 continuous transmission mode
 receiver cost may increase if an increase of the regeneration span offers a larger saving.
They translates into:
 filtering incoming phase noise is important
 the cost of circuitry with low noise generation is affordable
 fast acquisition is not important
then the preferred CDR implementation includes a phase comparator that behaves linearly, a low pass filter and a low noise oscillator whose frequency varies proportionally to the control signal. The PLL behaves very much as a 21 linear loop.
When more CDRs are chained so that their jitter transfer functions combine, then gain peaking must be minimum or absent: ζ >> 0.7.
Loop parameters[edit]
As seen in the previous page, the loop model is defined either by its performance parameters ω_{n2} and ζ , or by its design parameters G and τ_{f},

 where τ_{f} is the time constant of the loop filter and 1/ τ_{f} = ω_{f} its cut off frequency ; G is the open loop DC gain = G_{φ} * G_{f} * G_{VCO}.
As the application is reasonably well described by the model, the loop parameters offer a good enough description for most purposes.
The two sets of parameters are related:
Setting ω_{n2} and ζ  Setting G and τ_{f} 

G = ω_{n2} / 2ζ  ω_{n2}^{2} = G/τ_{f} 
τ_{f} = 1 / 2ζω_{n2}  ζ^{2} = 1 / 4τ_{f}G 
τ_{f} may vary within a +/ 30% range, but G may vary in a much wider range because it is linked also to the transition density.
If the filtering caracteristics ( τ_{f} ) are kept fixed, and just the open loop gain is varied:
 ω_{n21}^{2} = G / τ_{f} and ζ_{21}^{2} =1 / ( 4 G τ_{f})
 the 21 gets less damped with more gain, i.e. more damped with less gain.
 This behaviour of ζ_{21} with respect to the loop gain G explains why 21 is not used with bangbang phase detectors nor VCOs that have a highly variable gain.
 The interesting characteristics of the 21 (rejection of the signal jitter, that make it preferred for regenerator applications) depends on a good control of the damping ratio, ζ_{21} . ζ_{21}, in turn, depends on the loop gain G and decreases when G increases (risk of jitter peaking!): ζ_{21}^{2} =1 / ( 4 G τ_{f}).
It is important to keep in mind that the value of τ_{f} may vary in certain interval (e.g. +/ 30% because of manufacturing variability, ageing, power supply and temperature), but that G varies in a wider range because, in addition to the same factors that affect τ_{f}, G_{φ} in particular is affected by the transition density of the incoming signal.
Depending on the applications, D_{T} maybe considered as practically constant and equal to 50% (8B10B, 64/66 with scrambling, ...), or variable in a somewhat wider range around 50%.
In this second case, the loop gain G variability is correspondingly larger.
What is important is that this 21 loop has the lowest ζ when G is maximum, and therefore the design constraint is to use the maximum value of G to match the minimum value allowed for ζ. When transition density decreases and G decreases, then ζ increases and an overdamping of the characteristic must be accepted (the two poles of the characteristic of jitter transfer may become real and separate, degrading to some extent the valuable characteristics of this 21 loop. (It may also be pointed out that the 2  1 loop becomes unstable if the natural frequency ω_{n2} {that normally is about 1/2 ω_{f} or lower} gets close to ω_{f}. As ω_{n2} grows if the loop gain grows, it is not possible to use a bangbang detector because its gain varies very much with the phase difference it measures).
edit section[edit]
ζ close to 1 (0.7 to 1.3) at minimum D_{T}[edit]
The value of ζ shall be set by design close to 1 when D_{T} is at its minimum expected value.
In other words ζ during real operation (taking into account all factors, including manufacturing variations of each different unit) may be found anywhere in the range 0.7 to 3 or 4.

 If ζ was < 0.707, the jitter at frequencies around ω_{n2} would be amplified during the transit through the PLL as seen when studying the jitter transfer function of this loop, and more so for smaller values of ζ.

 Amplification of jitter may  if the input jitter at those frequencies is large enough to start with  accumulate when more identical regenerators are interconnected in a chain along the signal path (a not infrequent case in geographical networks) and eventually deteriorate the jitter tolerance beyond the acceptable boundary.

 When ζ >> 1, the loop behaves more and more like a first order loop. The sharp cutoff at about ω_{n2} , typical of a good 2nd order loop, smooths out, and the jitter at frequencies around ω_{n2} is less effectively rejected.
Similar indications are derived from the study of the error signal in this 21 loop.
 Large values of ζ ( >> 1) involve an appreciable error even at frequencies much lower than ;
 small values of ζ ( < 1.0) correspond to large overshoots of the phase error just above ω_{n2}.
Values of ζ between 0.7 and 1.3 are therefore an inevitable design choice. Other considerations that can be drawn from the study of the jitter tolerance function confirm the choice of this range of ζ values for the regenerator CDR design.
ω_{n2} and ω_{f}[edit]
The cutoff frequency of the loop filter block ω_{f} =1/τ_{f} fixes the bandwidth of the closed loop, apart from the minor adjustments of ζ as it varies within its allowed range).
The natural frequency ω_{n2} (which can also be seen as the jitter cutoff frequency of the CDR) is defined by the loop gain and by ω_{f} :
and can also be expressed as a function of just ζ and ω_{f} :
This simple formula tells that (in a 2^{nd} order PLL of type 1 where ζ_{21} must remain close to 1) the natural frequency ω_{n21} remains close to half the cutoff frequency of the loop filter!
VCO good centering and narrow jitter bandwidth
In the 2^{nd} order, type 1, loop, the VCO frequency mismatch f_{p} – f_{fr} becomes a sampling time error E_{s} according to:
(G= G_{φ}*G_{f}*G_{VCO}) For fixed open loop dc gain G and filter time constant τ_{f}, the jitter cutoff frequency ω_{n2} is:
It is easy to see that, for a 1st order type 1 loop: E_{s} = ((ω_{p} – ω_{fr}) / ω_{n1}
The same equation, rearranged, tells that the frequency mismatch and the maximum E_{s} define how tight the the loop jitter bandwidth can be:
It is easy to see that, for a 1st order type 1 loop: (ω_{n1}/ω_{p} ) = ((ω_{p} – ω_{fr}) /ω_{p}) / E_{s} )
For instance, if E_{s} is conservatively set as low as = 0.1 rad, then ω_{n2} can be : ω_{n2} ≃ 20 * (ω_{p} – ω_{fr}) .
As seen already about CDRs and parts per million of frequency mismatch, the free running frequency of a slave CDR may differ no more than 50 ppm from the frequency of its remote master (very low cost quartz crystal), or 10000 ppm (monolythic RC oscillator after EWS trimming), or even differ less than 1 ppm, still without big cost concerns (quartz for GPS receivers inside mobile phones). Less than 0.1 ppm is typical of professional equipment.
The four mentioned cases would set a respective minimum for the design choice of ω_{n2} at: 0.001 ω_{p} , 0.2 ω_{p} , 2 e5 ω_{p} , 2 ppm ω_{p} .
For a 21 loop when high transmission speed is involved, a jitterout/jitterin bandwidth of about 1/1000 of the bit rate is specified by most standards Clock Recovery Primer, Part 2 by Guy Foster, par.10: Survey of Clock Recovery Used in Selected Standards. Therefore the typical limit for ω_{n2} to respect is .....
ω_{n21} and ω_{n1}[edit]
In a 1^{st} order loop, the quantity ω_{n} = G tells how fast the loop reacts. The higher ω_{n}, the faster the loop response.
For the 2nd order loop it is difficult to relate ω_{n2} to how fast the loop reacts to a change. In the 2  1 loop, for ζ ≈ 1, and setting for sake of comparison the gain G equal for the two loops:
In other words a 2^{nd} order type 1 PLL (ζ ≈ 1) wold seem twice as “fast” as a 1st order PLL of the same gain!
But it can also be seen that, setting, for sake of comparison, ω_{n2} = ω_{n}, then the 2nd order type 1 loop is not practically slower than the 1st order loop!
 “Slow or fast” in the sentences above means both:
  slow or fast to acquire the lock condition
  slow or fast to drift to its free running frequency when the input signal disappears.
Note that the USR of the 1  1 loop model is plotted for two different values of ω_{n1}: ω_{n1} = ω_{n2} of the other two loops and 1/2 ω_{n1} = ω_{n2} of the other two loops
^{[2]} ^{[3]}
References[edit]
 ↑ ITUT G.813 (03/2003) Timing characteristics of SDH equipment slave clocks (SEC), Appendix II: Considerations on bandwidth requirements, noise accumulation and payload wander accumulation, II.1 Introduction.
 ↑ 1MA98: dB or not dB? Rohde & Schwarz Application Note http://www2.rohdeschwarz.com/file_5613/1MA98_4E.pdf
 ↑ Telecommunications: Glossary of Telecommunication Terms Federal Standard 1037C August 7, 1996 http://www.its.bldrdoc.gov/fs1037/fs1037c.htm
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