User:BORGATO Pierandrea

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Applications of the 1st order type 1 architecture[edit]

Jitter tolerance of the bang-bang 1 - 1 architecture[edit]

There always exists the possibility that the PLL is not able to follow a rapidly changing phase of its input because the rate of change of the VCO phase (i.e. the VCO frequency deviation) is limited. The PLL is "slew-rate" limited.

The slew-rate limits in fact correspond to the limits of the frequency range of the VCO.

In the case of the 1 - 1 architecture with bang-bang detector, this can only occur either because of its intrinsic limits or because of the limited range of its drive signal.

The 1 - 1 CDR is able to vary rapidly its frequency, because the loop can respond to an input phase step with a frequency step.

When the phase detector is a bang-bang, then the frequency step is always the largest possible jump, irrespectively of the input signal magnitude.

The steady star error shall also be kept into consideration: it appears at the CDR output as a frequency deviation from the free-running value: Es = fp - ffr.

The steps that the phase detector generates are consequently jumps to one of two (binary PD) to three (ternary PD values:

  • fmax
  • ffr ( if the PD is of "ternary" type)
  • fmin

and the VCO phase varies accordingly, and exhibits a constant slope during every period when the VCO frequency is constant. for short periods of constant slopes.

The input jitter jitter is tracked by bang-bang corrections that are triggered every time the input data stream has a level transition.

The PLL can track the input phase variations, but it cannot react faster than jumping to the frequency extremes of the VCO useful range (the frequency jump is a linear ramp of the PLL phase: the maximum ramp slope of a circuit is called the slew-rate ) . But if the phase of the input signal varies more rapidly than that, then a phase error appears and it may grow and possibly affect the CDR tolerance.

Sinusoidal input and slew-rate[edit]

This problem may be investigated also using a sinusoidal input phase jitter. The sinusoidal input is is also useful as the tolerance curve of the CDR is measured as a function of a sinusoidal input jitter whose frequency sweeps the frequency range of interest.

A sinusoidal phase function (of time in the case of jitter) has its maximum rate of variation at the zero crossings, and its maximum rate of variation is the tangent at the points of zero crossing. Its slope is Aω and can be obtained in the figure here below dividing the y-value AωT/4 by the x-value π/2ω :

Time diagram of a sinusoid of angular frequency ω and amplitude A,
with emphasis on the maximum slope equal to Aω, that relates to the slew-rate concept

Maximum phase slew-rate = maximum frequency deviation.

The max slope of phase variation that the VCO can rapidly generate in response to a constant (high or low) signal from the phase detector depends on the frequency of the VCO immediately before the correction and on the upper or lower frequency extreme of its range that it jumps to.

It also depends on the relative frequency of input transitions. When a transition generates a phase detection then the PD output stays at either of its significant states for one clock period. If a transition is missing, the PD stays at its intermediate state for a clock period. Averaging across a few clock period, the CDR behaves as if the PD gain was reduced (i.e. multiplied) by DT.

The open loop gain is defined as G = Gφ Gf GVCO.

If the input of the PLL is a sinusoidal jitter A sin (ωt), then its maximum slope is Aω and the loop will track it without phase error as long as:

GDT ≥ Aω
ω ≤ GDT/A
The sinusoidal jitter signal must be considered in conjunction with the steady state error because this type 1 loop compensates all frequency difference and wander with a shift of the bias level of the signal driving the VCXO. The slew rate slope of the CDR response to the next bang-bang corrections is consequently increased in one direction and reduced by the same amount in the other direction.
When tracking becomes difficult because the loop must operate close to its ability to track, the effort becomes evident in the reduction of the bang-bang duty-cycle. When the input jitter sinusoid crosses the zero, the PD output stays most often constant and indicates the onset of a phase error due to slewing.
Slewing can be defined as a contiguous sequence of ten or more identical phase-error indications.[1]
When the jitter frequency is too high for a correct tracking, the signal driving the VCO becomes a triangular saw-tooth of reduced amplitude.
The following figure illustrates the above condition in the signals inside a typical CDR of this type.

Acquisition and tracking example[edit]

Time diagram of waveforms at different nodes of a 1 - 1 CDR during acquisition and tracking.
Ternary bang-bang Phase detector.
The circuit operates very close to its jitter tolerance limit.
During the first 100 simulation steps (2.5 nsec) there is no input signal.
LOS is asserted and the CDR drifts at its free-running frequency, that is 5000 ppm ( 0.5% ) lower than the frequency of the remote transmitter.

Then the input signal appears (LOS is dis-asserted) with a "step" of +1.25 rad (useful to mark the beginning of the acquisition phase).
The input signal is flat in phase for the time being (no jitter yet).
The phase detector jumps from its intermediate state (that was forced by the LOS signal) to its upper state.
This jump propagates without delay to the VCO drive signal: the VCO jumps to its maximum frequency and its phase (i.e. the CDR output phase) increases linearly with its maximum possible slope.
The VCO maximum frequency is just 1.186e9 rad/sec (=18,870 ppm) higher than ωn , and this amount is the "rising" slew-rate of this CDR.
The "falling" slew-rate of this CDR is larger, and equal to -1.814e9 rad/sec (=-28,870 ppm), because ωfr is lower than than ωp (by 5000 ppm, i.e. by 3.142e8 rad/sec).
The output phase catches up with the input after 9.7 nsec.
The bang-bang detector, that has been frozen to its upper level during the catch-up transient, starts now its typical pattern of bang-bang frequent jumps.
Note that the frequent stops at its middle (ternary) level are not made evident by this simulation diagram, but the low transition density (0.125) is taken into account by a corresponding reduction of the PD gain.
It may also be remarked that, as long as the PD follows its typical bang-bang pattern, the distance in phase between input and output (=the error signal) remains very close to zero, and there is no evidence of the steady-state phase error typical of linear systems. In this condition the PD operates very close to its middle point, where its gain is extremely high: the steady stye error of a type 1 system can be computed as the angular frequency offset, divided by the open loop gain. As the gain is almost infinite, the error is almost zero.
When 700 simulation steps have elapsed (17.5 nsec), the input signal starts an additional sinusoidal jitter with an angular frequency of 3.42 108 rad/sec and a peak amplitude of 2.01 rad.
The sinusoidal component of the input jitter starts with its maximum slope (

Tolerance curve example[edit]

Frequency diagram of Jitter tolerance of a 1 - 1 CDR during acquisition and tracking.
Ternary bang-bang Phase detector.

It may be noted that the previous figures represent single points in this one.

The curves (obtained by simulations of each point)

Application of the 2-1 architecture[edit]

This architecture is used in practice for:

  • line regenerators, and for
  • slave clocks in long distance (=Telecom) networks.

The implementation with linear phase comparator and linear VCO is the typical case, as it best fits those target applications.

This is the architecture that produces the sharpest high frequency rejection (40 dB/dec), that is important when:

  • long distance links (=large distortions) affect the line signal with ISI and noise;
  • regenerators are connected in series to cover a very long distance span.

The use of a linear comparator (in contrast to a possible bang-bang alternative) generates very little noise.

As applications inside long distance equipment are less cost sensitive, the use of a linear comparator and of a linear VCOs with low noise and good linearity is possible.

The application of all PLL elements within their linear range allows to match the tight, demanding specifications that are typical of the Telecom world.

The cascading of of several CDRs in a long distance connection becomes possible because of the low noise generation, good input noise rejection and predictable characteristics.

The use of linear circuit blocks in these applications makes the linear model of the 2-1 architecture really and directly useful!

The ITU-T Recommendations generally indicate as a reference model the model that corresponds to the 2-1 architecture.

For instance:
“a SEC will generally mimic the behavior of a 2-nd order (type 1) linear analogue phase locked loop. This allows the use of the terms (equivalent) 3 dB bandwidth and (equivalent) damping factor, as they are used in analog PLL theory, irrespective of the fact that in the implementation of a SEC, digital and/or non-linear techniques may be used."[2]
( SEC: a SDH equipment slave clock)

In fact, when requirements are the following, like in a telecom networks:

  • continuous transmission mode
  • receiver cost may increase if an increase of the regeneration span offers a larger saving.

They translates into:

  • filtering incoming phase noise is important
  • the cost of circuitry with low noise generation is affordable
  • fast acquisition is not important

then the preferred CDR implementation includes a phase comparator that behaves linearly, a low pass filter and a low noise oscillator whose frequency varies proportionally to the control signal. The PLL behaves very much as a 2-1 linear loop.

When more CDRs are chained so that their jitter transfer functions combine, then gain peaking must be minimum or absent: ζ >> 0.7.

Loop parameters[edit]

As seen in the previous page, the loop model is defined either by its performance parameters ωn2 and ζ , or by its design parameters G and τf,

where τf is the time constant of the loop filter and 1/ τf = ωf its cut off frequency ; G is the open loop DC gain = Gφ * Gf * GVCO.

As the application is reasonably well described by the model, the loop parameters offer a good enough description for most purposes.

The two sets of parameters are related:

2nd order PLL of type 1: relations between performance and design parameters
 Setting ωn2 and ζ   Setting G and τf 
G = ωn2 / 2ζ ωn22 = G/τf
τf = 1 / 2ζωn2 ζ2 = 1 / 4τfG

τf may vary within a +/- 30% range, but G may vary in a much wider range because it is linked also to the transition density.

If the filtering caracteristics ( τf ) are kept fixed, and just the open loop gain is varied:

ωn212 = G / τf and ζ212 =1 / ( 4 G τf)
the 2-1 gets less damped with more gain, i.e. more damped with less gain.
This behaviour of ζ21 with respect to the loop gain G explains why 2-1 is not used with bang-bang phase detectors nor VCOs that have a highly variable gain.
  • The interesting characteristics of the 2-1 (rejection of the signal jitter, that make it preferred for regenerator applications) depends on a good control of the damping ratio, ζ21 . ζ21, in turn, depends on the loop gain G and decreases when G increases (risk of jitter peaking!): ζ212 =1 / ( 4 G τf).

It is important to keep in mind that the value of τf may vary in certain interval (e.g. +/- 30% because of manufacturing variability, ageing, power supply and temperature), but that G varies in a wider range because, in addition to the same factors that affect τf, Gφ in particular is affected by the transition density of the incoming signal.

Depending on the applications, DT maybe considered as practically constant and equal to 50% (8B10B, 64/66 with scrambling, ...), or variable in a somewhat wider range around 50%.

In this second case, the loop gain G variability is correspondingly larger.

What is important is that this 2-1 loop has the lowest ζ when G is maximum, and therefore the design constraint is to use the maximum value of G to match the minimum value allowed for ζ. When transition density decreases and G decreases, then ζ increases and an overdamping of the characteristic must be accepted (the two poles of the characteristic of jitter transfer may become real and separate, degrading to some extent the valuable characteristics of this 2-1 loop. (It may also be pointed out that the 2 - 1 loop becomes unstable if the natural frequency ωn2 {that normally is about 1/2 ωf or lower} gets close to ωf. As ωn2 grows if the loop gain grows, it is not possible to use a bang-bang detector because its gain varies very much with the phase difference it measures).

edit section[edit]

ζ close to 1 (0.7 to 1.3) at minimum DT[edit]

The value of ζ shall be set by design close to 1 when DT is at its minimum expected value.

In other words ζ during real operation (taking into account all factors, including manufacturing variations of each different unit) may be found anywhere in the range 0.7 to 3 or 4.

Amplification of jitter may - if the input jitter at those frequencies is large enough to start with - accumulate when more identical regenerators are interconnected in a chain along the signal path (a not infrequent case in geographical networks) and eventually deteriorate the jitter tolerance beyond the acceptable boundary.
  • When ζ >> 1, the loop behaves more and more like a first order loop. The sharp cutoff at about ωn2 , typical of a good 2nd order loop, smooths out, and the jitter at frequencies around ωn2 is less effectively rejected.

Similar indications are derived from the study of the error signal in this 2-1 loop.

Large values of ζ ( >> 1) involve an appreciable error even at frequencies much lower than \omega_{n2};
small values of ζ ( < 1.0) correspond to large overshoots of the phase error just above ωn2.

Values of ζ between 0.7 and 1.3 are therefore an inevitable design choice. Other considerations that can be drawn from the study of the jitter tolerance function confirm the choice of this range of ζ values for the regenerator CDR design.

ωn2 and ωf[edit]

The cut-off frequency of the loop filter block ωf =1/τf fixes the bandwidth of the closed loop, apart from the minor adjustments of ζ as it varies within its allowed range).

The natural frequency ωn2 (which can also be seen as the jitter cutoff frequency of the CDR) is defined by the loop gain and by ωf :

ωn22 = Gωf

and can also be expressed as a function of just ζ and ωf :

ωn21 = ωf /2ζ21

This simple formula tells that (in a 2nd order PLL of type 1 where ζ21 must remain close to 1) the natural frequency ωn21 remains close to half the cutoff frequency of the loop filter!

VCO good centering and narrow jitter bandwidth

In the 2nd order, type 1, loop, the VCO frequency mismatch fp – ffr becomes a sampling time error Es according to:

Es = (ωp – ωfr)/G

(G= Gφ*Gf*GVCO) For fixed open loop dc gain G and filter time constant τf, the jitter cut-off frequency ωn2 is:

ωn2 = G * 2ζ
Es = ((ωp – ωfr) * 2ζ ) / ωn2

It is easy to see that, for a 1st order type 1 loop: Es = ((ωp – ωfr) / ωn1

The same equation, rearranged, tells that the frequency mismatch and the maximum Es define how tight the the loop jitter bandwidth can be:

Es / 2ζ = (ωp – ωfr) / ωn2 = ((ωp – ωfr)/ωp) / (ωn2p)
n2 / ωp ) = ((ωp – ωfr) /ωp) / (Es /2ζ ))

It is easy to see that, for a 1st order type 1 loop: (ωn1p ) = ((ωp – ωfr) /ωp) / Es )

For instance, if Es is conservatively set as low as = 0.1 rad, then ωn2 can be : ωn2 ≃ 20 * (ωp – ωfr) .

As seen already about CDRs and parts per million of frequency mismatch, the free running frequency of a slave CDR may differ no more than 50 ppm from the frequency of its remote master (very low cost quartz crystal), or 10000 ppm (monolythic RC oscillator after EWS trimming), or even differ less than 1 ppm, still without big cost concerns (quartz for GPS receivers inside mobile phones). Less than 0.1 ppm is typical of professional equipment.

The four mentioned cases would set a respective minimum for the design choice of ωn2 at: 0.001 ωp , 0.2 ωp , 2 e-5 ωp , 2 ppm ωp .

For a 2-1 loop when high transmission speed is involved, a jitter-out/jitter-in bandwidth of about 1/1000 of the bit rate is specified by most standards Clock Recovery Primer, Part 2 by Guy Foster, par.10: Survey of Clock Recovery Used in Selected Standards. Therefore the typical limit for ωn2 to respect is .....

ωn21 and ωn1[edit]

In a 1st order loop, the quantity ωn = G tells how fast the loop reacts. The higher ωn, the faster the loop response.

For the 2nd order loop it is difficult to relate ωn2 to how fast the loop reacts to a change. In the 2 - 1 loop, for ζ ≈ 1, and setting -for sake of comparison- the gain G equal for the two loops:

ωn21 = 2ζ21 G
ωn21 ≈ 2 ωn1

In other words a 2nd order type 1 PLL (ζ ≈ 1) wold seem twice as “fast” as a 1st order PLL of the same gain!

But it can also be seen that, setting, for sake of comparison, ωn2 = ωn, then the 2nd order type 1 loop is not practically slower than the 1st order loop!

“Slow or fast” in the sentences above means both:
- slow or fast to acquire the lock condition
- slow or fast to drift to its free running frequency when the input signal disappears.
The following figure contrasts the Unit Step Responses of the 3 important PLL models:
USRs of the 3 important loop models.
2 - 1 and 2 - 2 are plotted for natural undamped frequency = 6.28 Grad/sec and ζ = 1
1 -1 is plotted for both natural frequency = 6.28 Grad/sec and 3.14 Grad/sec.

Note that the USR of the 1 - 1 loop model is plotted for two different values of ωn1: ωn1 = ωn2 of the other two loops and 1/2 ωn1 = ωn2 of the other two loops

[3] [4]


  1. Richard C.Walker article, IV. SLOPE OVERLOAD, B. Expression for Slope Overload, page 7.
  2. ITU-T G.813 (03/2003) Timing characteristics of SDH equipment slave clocks (SEC), Appendix II: Considerations on bandwidth requirements, noise accumulation and payload wander accumulation, II.1 Introduction.
  3. 1MA98: dB or not dB? Rohde & Schwarz Application Note
  4. Telecommunications: Glossary of Telecommunication Terms Federal Standard 1037C August 7, 1996

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