User:BORGATO Pierandrea

Oscillator controlled in frequency ("first order slave CDR")

This example (its architecture is shown on the top left in the Figure above) has value in that it introduces this type of architecture and allows an easy derivation of the model equations.

For slave CDR applications though, PLLs of the second order are preferred and this one can only be found in the simplest, undemanding, applications.

The second architecture of PLL in the figure above is a slight variant of the first, and is not important for CDR loops. It can be important instead as model of the [[w:Delay-locked loop|DLL].

The model is described in detail in a page dedicated to the 1^st order, type 1 architectures later on in this book, owing to the practical importance of its phase-aligner variant.

To be able and contrast this architecture with the others in this page of examples, its jitter transfer function, its response to a unit step variation of the input signal phase and its jitter tolerance function ( The jitter tolerance function ) are shown in the Figures here below.

Their relevant equations are:

Magnitude of the transfer function: $\left |\tfrac{Y(s)}{X(s)}\right | = \left |\tfrac{1}{(1 + j\omega/G)}\right | = \tfrac{1}{\sqrt{1+(\omega/G)^2}}$

Unit step response: ${\color{Black}1 - e^{-\omega_n t}}$

Magnitude of the jitter tolerance: $\left |X(j\omega)\right |_{\left |\Epsilon(j\omega)\right | = \Phi_{leo} }$ = $\Phi_{leo} \sqrt{\tfrac{( 1 + \omega^2/\omega_n^2)}{\left ( \omega^2/\omega_n^2\right )}}$ , ( where Φ_leo is the lateral eye opening expressed in radian) .

This architecture clearly shows:

• a medium jitter tolerance, with the 20 dB/decade asymptote towards zero frequency. It comes from the pole 1/s present in the forward path of the control loop. This is a minimum characteristic when the CDR must operate as a slave and track frequencies that can wander around their nominal value;
• a medium (20 dB/decade) jitter filtering towards high frequencies;
• only one degree of liberty for the designer (that is G in the figures above, i.e. the open loop d.c. gain).

All these characteristics together make this architecture not preferred in actual designs of slave CDRs. For these, the second order, type 1 or type 2, architectures are chosen instead, depending on the requirements and on the technology available for the specific application.

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It is easy to see that, for a 1st order type 1 loop: (ω_n1/ω_p ) = ((ω_p – ω_fr) /ω_p) / E_s )

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Titolo

Left side Note.

BORGATO Pierandrea (talk) 07:48, 28 September 2010 (UTC)

Delete - delete work

The unit step response