Talk:X86 Assembly/Protected Mode

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according to preliminary specification of amd 5x86 processor register cr0 contains also bit CD which let to disable internal cache


This page doesn't include all of the used bits within the CR0 register.

- Bit 16 - Write Protection
- Bit 18 - Alignment Mask
- Bit 29 - Not Write
- Bit 30 - Cache Disable
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