Programmable Logic/VHDL Operators

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< Programmable Logic/VHDL

Programmable Logic

This page is going to discuss VHDL Operators.

Some abbreviations used in this text:

• int - integer, a data type
• sl - std_logic, a data type (in most cases replacable with bit)
• slv - std_logic_vector, a data type (in most cases replacable with bit_vector)
• slu - std_logic_unsigned - a part of library ieee.
• sls - std_logic_signed - a part of library ieee.
• iff - "if and only if"

Contents 1 Logical Operators 2 Arithmetic Operators 3 Relational Operators 4 Shift and Rotate

[edit] Logical Operators

This list is far from complete.

operator	examples	description
sl and sl	a_sl <= b_sl and c_sl a_sl <= ieee.std_logic_1164."and"(b_sl, c_sl);	a_sl will be '1' iff both b_sl and c_sl is '1'
slv and slv	a_slv <= b_slv and c_slv a_slv <= ieee.std_logic_1164."and"(b_slv, c_slv);	Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits)
sl or sl	a_sl <= b_sl or c_sl a_sl <= ieee.std_logic_1164."or"(b_sl, c_sl);	a_sl will be '1' iff at least one of b_sl and c_sl is '1'.
slv or slv	a_slv <= b_slv or c_slv a_slv <= ieee.std_logic_1164."or"(b_slv, c_slv);	Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits)
sl xor sl	a_sl <= b_sl xor c_sl a_sl <= ieee.std_logic_1164."xor"(b_sl, c_sl);	a_sl will be '1' iff exactly one of b_sl and c_sl is '1'.
slv xor slv	a_slv <= b_slv xor c_slv a_slv <= ieee.std_logic_1164."xor"(b_slv, c_slv);	Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits)
not sl	a_sl <= not b_sl a_sl <= ieee.std_logic_1164."not"(b_sl);	a_sl will be inverse of b_sl, that is '1' iff b_sl = '0'.
not slv	a_slv <= not b_slv a_slv <= ieee.std_logic_1164."not"(b_slv);	Applied to each respectively bits in a_slv, b_slv. a_slv, b_slv must have equal length (e.g. 8 bits)
sl nand sl	a_sl <= b_sl nand c_sl a_sl <= ieee.std_logic_1164."nand"(b_sl, c_sl);	a_sl will be '1' iff at least one of b_sl and c_sl is '0'. Equivalent to not (sl and sl)
slv nand slv	a_slv <= b_slv nand c_slv a_slv <= ieee.std_logic_1164."nand"(b_slv, c_slv);	Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits)
sl nor sl	a_sl <= b_sl nor c_sl a_sl <= ieee.std_logic_1164."nor"(b_sl, c_sl);	a_sl will be '1' iff both b_sl and c_sl is '0'. Equivalent to not (sl or sl)
slv nor slv	a_slv <= b_slv nor c_slv a_slv <= ieee.std_logic_1164."nor"(b_slv, c_slv);	Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits)
sl xnor sl	a_sl <= b_sl xnor c_sl a_sl <= ieee.std_logic_1164."xnor"(b_sl, c_sl);	a_sl will be '1' iff both b_sl and c_sl is either '1' or '0'. Equivalent to not (sl xor sl)
slv xnor slv	a_slv <= b_slv xnor c_slv a_slv <= ieee.std_logic_1164."xnor"(b_slv, c_slv);	Applied to each respectively bits in a_slv, b_slv, c_slv. a_slv, b_slv, c_slv must have equal length (e.g. 8 bits)

[edit] Arithmetic Operators

[edit] Relational Operators

[edit] Shift and Rotate

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