Programmable Logic/VHDL General Syntax

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VHDL's syntax is derived from ADA. It is strongly typed and case insensitive.

Identifiers[edit]

An identifier in VHDL must begin with a letter and can be any combination of letters, digits, and underscore (_).

Comments[edit]

A comment in VHDL is denoted with a "--":

-- Assign the current value to the next state value
sQ_next <= sQ;

Everything after the "--" to the end of the line is considered a comment.

-- This is a valid comment
sQ_next <= sQ; -- This is also a valid comment

Keywords[edit]

The following words are VHDL keywords and cannot be used for identifiers (signal names, process names, entity names, etc...)

VHDL '87[edit]

This is an incomplete list...

and, or, nor, xor, not, architecture, entity, is, process, procedure,
function, type, subtype, array, begin, end, if, elsif, end, case, when,
others, configuration, package, constant, signal, variable, component,
label, port, generic, all, nand, nor, abs, generate, in, out, inout,
buffer, linkage, bus, library, null, loop, for, body, to, downto

VHDL '93[edit]

VHDL '87 keywords and:

group, impure, inertial, literal, postponed, pure, reject, rol, ror,
shared, sla, sll, sra, srl, unaffected, xnor

VHDL '00[edit]

VHDL '93 and '87 keywords, additionally:

generate map, access, mod, severity, units, after, until, alias, guarded,
use, new, disconnect, next, protected, attribute, record, of, register, on,
block, exit, open, rem, transport, report, file, return

VHDL '02[edit]

VHDL '08[edit]