Programmable Logic/VHDL Data Types
This page is going to discuss some of the basic data types of VHDL.
0 and 1
Boolean is another predefined type that has value FALSE and TRUE.
This integer values varies from -2147483648 to 2147483648.
User defined types
Arrays allow many identical data types to be created. These data types are accessed using a number called an index. An example array declaration is as follows:
type tIntegerArray is array ( 7 downto 0 ) of integer;
This declaration will create a new data type that is an array. This array will contain 8 integers with indexes of the numbers 7, 6, 5, ... 1, 0.
Once declared, an array can be used as any data type would:
signal sBunchOfInts: tIntegerArray;
A individual element of an array can then be accessed with using ():
sBunchOfInts(2) <= 4;
Many newer synthesis tools will expand arrays into many signals with the array appended on the end of the signal name as a suffix. This helps organize repetitive VHDL code and allows std_logic_vectors to be used in for generate and for loops in VHDL code. This reduces the lines of code, and helps organize the code and make it more maintainable.
Records allow one to group related data types together. It is analogous to a "struct" in C programming. Although records do not add any additional functionality to a module, they do assist in organizing code and making it more maintainable. Here is an example declaration of a record:
type rStatus is record read_failure: std_logic; write_failure: std_logic; failure_count: std_logic_vector( 7 downto 0 ); end record;
Once the record is declared, a port, signal, or variable can then be declared using the record as a type:
decoder_status : in rStatus;
signal sStatus: rStatus; signal sStatus_next: rStatus;
variable vStatus: rStatus;
The record type can then be accessed using the ".":
sStatus_next.failure_count <= sStatus.failure_count + x"01";
Although they used to be limited to test benches and other simulation only VHDL modules, many of the newer synthesis tools will correctly expand record types out into their individual parts. This allows the organizational and maintainability benefits of record types to be used in RTL and other synthesizable code.
The ieee.std_logic_1164 library was created to give a standard representation of digital circuit logic values. It defines the type std_logic and the various manipulations of std_logic (and, or, not, etc...). When writing VHDL for a synthesizable circuit, this is usually a required library.
Defined Data Types
|std_logic||'U' - Uninitialized
'X' - Forcing Unknown
'0' - Forcing 0
'1' - Forcing 1
'Z' - High Impedance
'W' - Weak Unknown
'L' - Weak 0
'H' - Weak '1'
'-' - Don't care
|'1', '0', 'Z'||std_logic is an enumeration that represents the different possible states of a signal in a logic circuit|
|std_logic_vector||A string of std_logic such as "01001XZ"||Strings containing '1', '0', and/or 'Z'||std_logic_vector is a string of std_logic values. It allows the easy representation of buses and other multiple signal values|
this is not a standard library, despite being in the "ieee" library. Always use numeric_std instead.