MIPS Assembly/Instruction Formats

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MIPS Assembly


This page is going to discuss the implementation details of the MIPS instruction formats.

Contents

[edit] R Instructions

R instructions are used when all the data values used by the instruction are located in registers.

All R-type instructions have the following format:

OP rd, rs, rt

Where "OP" is the mneumonic for the particular instruction. rs, and rt are the source registers, and rd is the destination register. As an example, the add mneumonic can be used as:

add $s1, $s2, $s3

Where the values in $s2 and $s3 are added together, and the result is stored in $s1. In the main narrative of this book, the operands will be denoted by these names.

[edit] R Format

Converting an R mneumonic into the equivalent binary machine code is performed in the following way:

opcode rs rt rd shift funct
opcode
The opcode is the machinecode representation of the instruction mneumonic. Several related instructions can have the same opcode. The opcode field is 6 bits long (bit 26 to bit 31).
rs, rt, rd
The numeric representations of the source registers and the destination register. These numbers correspond to the $X representation of a register, such as $0 or $31. Each of these fields is 5 bits long. (25 to 21, 20 to 16, and 15 to 11, respectively).
Shift
Used with the shift and rotate instructions, this is the amount by which the source operand rs is rotated/shifted. This field is 5 bits long (6 to 10).
Funct
For instructions that share an opcode, the funct parameter contains the necessary control codes to differentiate the different instructions. 6 bits long (0 to 5). Example: Opcode 0x00 accesses the ALU, and the funct selects which ALU function to use.

[edit] Function Codes

[edit] Shift Values

[edit] I Instructions

I instructions are used when the instruction must operate on an immediate value and a register value. Immediate values may be a maximum of 16 bits long. Larger numbers may not be manipulated by immediate instructions.

I instructions are called in the following way:

OP rt, rs, IMM

Where rt is the destination register, rs is the source register, and IMM is the immediate value. The immediate value can be up to 16 bits long. For instance, the addi instruction can be called as:

addi $s1, $s2, 100

Where the value of $s2 plus 100 is stored in $s1.

[edit] I Format

I instructions are converted into machine code words in the following format:

opcode rs rt IMM
Opcode
The 6-bit opcode of the instruction. In I instructions, all mneumonics have a one-to-one correspondence with the underlying opcodes. This is because there is no funct parameter to differentiate instructions with an identical opcode. 6 bits (26 to 31)
rs, rt
The source and destination register operands, respectively. 5 bits each (21 to 25 and 16 to 20, respectively).
IMM
The 16 bit immediate value. 16 bits (0 to 15).

[edit] J Instructions

J instructions are used when a jump needs to be performed. The J instruction has the most space for an immediate value, because addresses are large numbers.

J instructions are called in the following way:

OP LABEL

Where OP is the mneumonic for the particular jump instruction, and LABEL is the target address to jump to.

[edit] J Format

J instructions have the following machine-code format:

Opcode Address
Opcode
The 6 bit opcode corresponding to the particular jump command. (26 to 31).
Address
A 26-bit address of the destination. (0 to 25).

[edit] FR Instructions

FR instructions are similar to the R instructions described above, except they are reserved for use with floating-point numbers.

[edit] FI Instructions

FI instructions are similar to the I instructions described above, except they are reserved for use with floating-point numbers.

[edit] Opcodes

The following table will contain a listing of MIPS instructions and the corresponding opcodes. Opcode and funct numbers are all listed in hexidecimal.

Mneumonic Type Opcode Funct
add R 0x00 0x20
addi I 0x08 NA
addiu I 0x09 NA
addu R 0x00 0x21
and R 0x00 0x24
andi I 0x0C NA
beq I
bne I
div
divu
j J
jal
jr R 0x00 8
lbu
lhu
lui
lw I
mfhi
mflo
mfc0
mult
multu
nor R 0x00 0x27
xor R 0x00 0x26
or R 0x00 0x25
ori I 0x0D NA
sb I
sh I
slt
slti
sltiu
sltu
sll
srl
sub R 0x00 0x22
subu R 0x00 0x23
sw I
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