MIPS Assembly/Instruction Formats
This page is going to discuss the implementation details of the MIPS instruction formats.
R instructions are used when all the data values used by the instruction are located in registers.
All R-type instructions have the following format:
OP rd, rs, rt
Where "OP" is the mnemonic for the particular instruction. rs, and rt are the source registers, and rd is the destination register. As an example, the add mnemonic can be used as:
add $s1, $s2, $s3
Where the values in $s2 and $s3 are added together, and the result is stored in $s1. In the main narrative of this book, the operands will be denoted by these names.
Converting an R mnemonic into the equivalent binary machine code is performed in the following way:
- The opcode is the machinecode representation of the instruction mnemonic. Several related instructions can have the same opcode. The opcode field is 6 bits long (bit 26 to bit 31).
- rs, rt, rd
- The numeric representations of the source registers and the destination register. These numbers correspond to the $X representation of a register, such as $0 or $31. Each of these fields is 5 bits long. (25 to 21, 20 to 16, and 15 to 11, respectively). Interestingly, rather than rs and rt being named r1 and r2 (for source register 1 and 2), the registers were named "rs" and "rt" because t comes after s in the alphabet. This was most likely done to reduce numerical confusion.
- Shift (shamt)
- Used with the shift and rotate instructions, this is the amount by which the source operand rs is rotated/shifted. This field is 5 bits long (6 to 10).
- For instructions that share an opcode, the funct parameter contains the necessary control codes to differentiate the different instructions. 6 bits long (0 to 5). Example: Opcode 0x00 accesses the ALU, and the funct selects which ALU function to use.
I instructions are used when the instruction must operate on an immediate value and a register value. Immediate values may be a maximum of 16 bits long. Larger numbers may not be manipulated by immediate instructions.
I instructions are called in the following way:
OP rt, rs, IMM
Where rt is the destination register, rs is the source register, and IMM is the immediate value. The immediate value can be up to 16 bits long. For instance, the addi instruction can be called as:
addi $s1, $s2, 100
Where the value of $s2 plus 100 is stored in $s1.
I instructions are converted into machine code words in the following format:
- The 6-bit opcode of the instruction. In I instructions, all mneumonics have a one-to-one correspondence with the underlying opcodes. This is because there is no funct parameter to differentiate instructions with an identical opcode. 6 bits (26 to 31)
- rs, rt
- The source and destination register operands, respectively. 5 bits each (21 to 25 and 16 to 20, respectively).
- The 16 bit immediate value. 16 bits (0 to 15). This value is usually used as the offset value in various instructions, and depending on the instruction, may be expressed in two's complement.
J instructions are used when a jump needs to be performed. The J instruction has the most space for an immediate value, because addresses are large numbers.
J instructions are called in the following way:
Where OP is the mneumonic for the particular jump instruction, and LABEL is the target address to jump to.
J instructions have the following machine-code format:
- The 6 bit opcode corresponding to the particular jump command. (26 to 31).
- A 26-bit address of the destination. (0 to 25).
FR instructions are similar to the R instructions described above, except they are reserved for use with floating-point numbers:
FI instructions are similar to the I instructions described above, except they are reserved for use with floating-point numbers:
The following table contains a listing of MIPS instructions and the corresponding opcodes. Opcode and funct numbers are all listed in hexadecimal.
||Add Unsigned Immediate||I||0x09||NA|
||Bitwise AND Immediate||I||0x0C||NA|
||Branch if Equal||I||0x04||NA|
||Branch if Not Equal||I||0x05||NA|
||Jump to Address||J||0x02||NA|
||Jump and Link||J||0x03||NA|
||Jump to Address in Register||R||0x00||0x08|
||Load Byte Unsigned||I||0x24||NA|
||Load Halfword Unsigned||I||0x25||NA|
||Load Upper Immediate||I||0x0F||NA|
||Move from HI Register||R||0x00||0x10|
||Move from LO Register||R||0x00||0x12|
||Move from Coprocessor 0||R||0x10||NA|
||Bitwise NOR (NOT-OR)||R||0x00||0x27|
||Bitwise XOR (Exclusive-OR)||R||0x00||0x26|
||Bitwise OR Immediate||I||0x0D||NA|
||Set to 1 if Less Than||R||0x00||0x2A|
||Set to 1 if Less Than Immediate||I||0x0A||NA|
||Set to 1 if Less Than Unsigned Immediate||I||0x0B||NA|
||Set to 1 if Less Than Unsigned||R||0x00||0x2B|
||Logical Shift Left||R||0x00||0x00|
||Logical Shift Right (0-extended)||R||0x00||0x02|
||Arithmetic Shift Right (sign-extended)||R||0x00||0x03|